JPS6286868A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that suppresses short channel effects and realizes a short gate length by a self-alignment method.

BACKGROUND OF THE INVENTION FIG. 2 shows an example of a conventional manufacturing method of a field effect transistor (hereinafter referred to as FET) in which a short gate length is realized by a self-alignment method. In FIG. 2, a first layer of silicon oxide film and a second layer of aluminum metal film are deposited on a GaAs substrate 1 on which an active layer 2 has been formed in advance. A dummy gate 6 is formed of a first layer of silicon oxide film 6 and a second layer of aluminum metal film 4. Then, this dummy gate 6
The homic layer 3 is formed by ion-implanting high-concentration impurities using as a mask and performing heat treatment.

In FIG. 2(b), the first layer silicon oxide film 5 of the dummy gate 6 is plasma etched using CF4 gas to reduce the width in the channel length direction to form a T-shaped dummy gate 6'.

In FIG. 2 (→), the second layer of the aluminum metal film 4 of the dummy gate 6' is removed, and a gate electrode 7 is formed by a planarization lift-off method using a resist 7'.

In FIG. 2 (→), an ohmic electrode 8 is formed using photorin technology and a lift-off method, and an FET is realized.

Problems to be Solved by the Invention In the conventional method, a dummy gate is used as a mask, and the source,
When forming a high concentration impurity layer in the drain region, the impurity implanted at a high concentration due to annealing after ion implantation diffuses into the active layer, causing a short channel effect, and the FET
This results in fluctuations in the threshold voltage and a decrease in reverse breakdown voltage. Also,
For dummy gates, it is difficult to control the etching of the first layer of the dummy gate to shorten the gate length, resulting in poor yield.

Means for Solving the Problems The present invention has been made in view of this problem, and it is possible to suppress the diffusion of the high concentration impurities by forming the high concentration impurity layer in the source and drain regions by epitaxial growth. , a short gate length is achieved by forming the gate electrode using a self-alignment method.

Function: According to the method for manufacturing a semiconductor device of the present invention, short channel effects are suppressed, and fluctuations in the threshold voltage of the FET and decreases in reverse breakdown voltage are suppressed. Further, since an FET with a short gate length can be realized without using a dummy gate, deterioration in yield can be reduced.

EXAMPLES Hereinafter, the method for manufacturing a semiconductor device of the present invention will be explained based on examples. FIG. 1 shows an embodiment of the present invention. Figure 1 (
In a), a silicon oxide film 13 of 3000 layers is deposited on a GaAg semi-insulating GaAs substrate 11 on which an n-type active layer 12 with an impurity concentration of 2XI Q"m-3 is formed, and a source is formed by photoetching.

A window 14 is opened in the drain region.

Figure 1 (in 11, Ga is a solution and As C1l
GaAg is epitaxially grown by vapor phase decomposition of s).Growth temperature is 800°C to 7.
Epitaxial growth is performed on the window 14 of the north drain region at 20° C. to form a T-shaped epitaxial growth layer 16. At this time, sulfur (S), which is an n-type impurity, is introduced from the gas phase as hydrogen sulfide.

In FIG. 1(C), the silicon oxide film 13 is removed with hydrofluoric acid, and a plasma CVD silicon nitride film is deposited on the entire surface.
A silicon nitride film 16 is formed on the sidewall of the epitaxial layer 16 by reactive ion etching using CF4 gas.

In FIG. 1 (4), a gate electrode 17 and an ohmic electrode are formed by conventional photolithography and lift-off methods.

In addition, although the halogen vapor phase epitaxy method was used for the epitaxial growth layer in the examples of the present invention, other vapor phase epitaxy methods may be used.

A growth method such as liquid phase bimolecular beam may also be used.

Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, it is possible to suppress fluctuations in the threshold voltage and decrease in reverse breakdown voltage of an FET in which short channel effects are suppressed. Further, since an FET with a short gate length can be realized without using a dummy gate, deterioration in yield can be reduced.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing an FET, which is an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a process sectional view showing a method for manufacturing an FET using a conventional self-alignment method. 11...GaAs semi-insulating substrate, 12...
...Active layer, 13...Silicon oxide film, 14.
...North drain area window, 16...
・High concentration impurity epitaxial growth layer, 16...
・Silicon nitride film, 17...Gate electrode, 18
...Ohmic electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (C/) Figure 2

Claims (2)

[Claims] (1) A step of forming a semiconductor layer of one conductivity type on one main surface of a semiconductor substrate, a step of depositing a first insulating film on the semiconductor layer, and a step of depositing the first insulating film in the source and drain regions. a step of forming a highly concentrated impurity layer of one conductivity type in the source and drain regions by epitaxial growth;
A method for manufacturing a semiconductor device comprising the steps of: forming a second insulating film only on the sidewalls of the high concentration impurity layer in the source and drain regions on the gate region side; and forming electrodes in the gate, source and drain regions. . (2) The method of manufacturing a semiconductor device according to claim 1, wherein the high concentration impurity layer of the source and drain regions formed by epitaxial growth has a T-shape.