JPS6286920A - decoder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a decoder, and particularly to an oversampled DA.
This invention relates to a decoder using a converter.

[Background of the invention]

As a method of converting a digital signal into an analog signal, there is an oversampling DA conversion method described in Japanese Patent Application Laid-Open No. 59-210725. This method first converts a high-resolution digital input signal with a long word length into a low-resolution digital signal by quantizing it.
Next, this digital signal is converted into an analog signal. At this time, in order to minimize S/N deterioration due to quantization within the desired signal frequency band, DAf is
It is necessary to perform a conversion operation.

Figure m3 shows the configuration of a conventional decoder using a ΔΣ oversampling type DA converter. In FIG. 6, the ratio signal input to signal input terminal 1 is input to interpolation filter 2'
converted into a high-speed digital signal by n1, then converted into an analog signal by an oversampled DA converter n,
The signal is output to the signal output terminal 5.

The oversampled DA converter 6 is composed of an oversampled modulator 3 and a DA converter 4', and the oversampled modulator 3 is composed of an adder 31, an integrator 52, and a quantizer 35. There are n.

The signal input to the signal input terminal 1 is normally a signal that has undergone digital signal processing at a previous stage (not shown), and its sampling rate is determined by the processing speed of the signal processing section.
Not fast enough for the desired signal frequency band (usually the sampling frequency is 32 KHz to 64 KHz)
II) o Therefore, input to signal input terminal 1 n
It is necessary to perform i-fold signal interpolation and increase the sampling rate.

However, since this interpolation operation generates noise, it is necessary to remove the noise using an interpolation filter 2'. The high-resolution digital signal output from the interpolation filter 2' is converted into an analog signal by an auto-sample type DA converter 6.

At this time, since the output of the oversampling modulator B is a low-resolution digital signal, a low-resolution DA converter 4' can be used, and the node configuration is simplified.

Let us now consider a configuration in which the transfer function of the interpolation filter 2' is expressed by the following equation (1). Equation (1) is used when converting a signal with a sampling period of 32T into a high-speed digital signal with a sampling period of T.

-Z-32 H(z)=(ding)ma However, 2−′=θ−−− T: sampling period It is.

In equation (1), the first term can be constructed by a differentiating circuit, and the second term
The first term can be constructed with a sample-and-hold circuit, and the third term can be constructed with a digital complete integration circuit.

FIG. 4 shows an example of the configuration of the interpolation filter 2'. In the figure, 21 is a differentiator, 22 is a sample-and-hold circuit, and 23 is an integrator. Next, 7 is a switch control circuit, 41 is a reference voltage supply terminal, 42° 45 is a two-shot capacitor circuit, 45 425° 455 is a capacitive element, 44
Fi squashing amplifiers 421 to 424 and 451 to 454 are switches.

The sampling period input to signal input terminal 1 is 32T.
The digital signal is interpolated by an interpolation filter 2' and converted into a high-speed digital signal with a sampling period of n. This signal is a high resolution digital signal,
The signal is quantized by an oversampled modulator 6 and converted into a low-resolution digital signal. Quantizer 33
The output is a ΔΣ modulated n-th order low resolution digital signal.

This signal is input to the switch control circuit 7. This switch control circuit 7 switches 421 to 424° 451
454 and outputs an analog signal corresponding to the output of the quantizer 33 to the output terminal 5. Here, the switched capacitor circuit 45 is a circuit for resetting the output value.

As described above, conventional decoders require a large amount of hardware and are expensive.

[Purpose of the invention]

An object of the present invention is to provide a decoder with a small amount of hardware and a simple circuit configuration.

[Summary of the invention]

In order to achieve the above object, the present invention provides a decoder consisting of an interpolation filter that includes a perfect integral factor in the transfer function and an oversampled DAf converter. A signal generator is constructed using a digital filter having a transfer characteristic expressed by a factor other than a factor, an oversampling modulator that modulates the output of the digital filter, and an integrator that performs analog integration of the output result of the modulator. This aims to simplify the circuit configuration and reduce node distortion without changing the transfer characteristics.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

There are many transfer functions for the interpolation filter in addition to those shown in equation (1) below. Here, it is assumed that it is represented by a general formula as shown in the following formula (2).

Then, Z = e js'! T: Sampling period' A(Z): This is the next part of the transfer function of the interpolation filter excluding the perfect integral factor.

The first term of equation (2) can be constructed by a digital complete integration circuit as described above. However, in this embodiment, the first term f s
The circuit configuration is such that analog integration is performed after DAK conversion. The second term of equation (2) is configured by a digital filter. FIG. 1 shows an example of its configuration.

In the same figure, 1 is the signal input terminal, and 2 is the second terminal in equation (2).
A digital filter that constitutes the A (Z) section,
6 is an oversampling type DAf converter, 4 is an analog integrator that constitutes the first term of equation (2), and 5 is a signal output terminal. In this configuration, the transfer characteristic of the analog integrator 4 is equivalent to the first term of equation (2).

Accordingly, the transfer characteristics of the post-signal unit as a whole are equivalent to the following case where all the interpolation filters are constructed digitally. Friend, in this configuration, the DAf converter and integrator 4 of the oversampling DA converter 6 are composed of suinotito capacitor circuits, and n can be easily constructed. A specific example is shown in FIG. Here, it is assumed that the transfer function of the interpolation filter is shown in equation (1) above, and that a Δ1'' type DAK converter, which is one of the methods, is used as the oversampling type DA converter.

Regarding the configuration of the interpolation filter, equation (1) is transformed as shown in the following equation.

H(z)=-sweat)2=-A(z) ・・・・・・・・・
(3) 1-z-' Configure the first item of A (z) in equation (3) with a differential circuit,
The second item consists of a sample and hold circuit.

In FIG. 2, 21 is a differentiator, 22 is a sample-and-hold circuit, 3 is an overlength modulator, and 4 is f
An integrator that converts the y4 result into an analog signal and integrates the entire value; 7 is a switch control circuit; 211.51 is an adder; 212 is a delay element that delays by time 52T; 62 is an integrator; and 36 is a quantizer. , 41 is a reference voltage input bubble, 42
is a switched capacitor circuit, 43. 425 is a capacitor element, 44 is an operational amplifier, and 421 to 424 are switches.

In such a configuration, the signal input to input terminal 1 is
After being differentiated by a differentiating circuit 21, the sample and hold circuit 22 converts the signal into a high-speed digital signal with a sampling rate of 32 times. This signal is modulated by an oversampled modulator 6. The signal output from the modulator 3 is ΔΣ
A modulated signal, usually consisting of several bits. FIG. 2 shows a configuration in which the output of the modulator is binary, -1 and +1. This output is input to the switch control circuit 7. In the switch control circuit 7, the switches 421 to
424, the next analog signal is integrated in the integrator 4 and output to the signal output terminal 5 according to the output of the f adjuster 3.

As described above, according to the present embodiment, the integration function of the interpolation filter is performed by an analog circuit, so the amount of hardware for the interpolation filter configured by a digital circuit is reduced, and it is not necessary in the conventional technology. A reset circuit for the DA converter is not required, and the amount of hardware for the DA converter is also reduced.

〔Effect of the invention〕

According to the present invention, the amount of hardware of the entire decoder is reduced, resulting in a reduction in cost.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of a decoder according to an embodiment of the present invention,
2 is a detailed block diagram of the decoder shown in FIG. 1, FIG. 6 is a block diagram of a conventional decoder, and FIG. 4 is a detailed block diagram of the decoder shown in FIG. 3. 2...Digital filter, 3...Oversampling type f adjuster, 4...Integrator, 6...Oversampling type DA converter. /7 emotion (゛

Claims (1)

[Claims] A digital filter having a transfer characteristic expressed by a factor excluding the perfect integral factor in the transfer function of an interpolation filter, an oversampling modulator that modulates the output of the digital filter, and analog integration of the output of the oversampling modulator. A decoder comprising an oversampling type DA converter configured with an integrator.