JPS6286933A - Phase synchronizing system - Google Patents

Abstract

PURPOSE:To prevent occurrence of twice reading and slip in elastic store by making phase relation of read reset pulse of an elastic store and read reset pulse maximum distance at the time of initial setting. CONSTITUTION:The system consists of a frame synchronizing circuit, a WR, WI forming counter, an elastic store, a comparator circuit, an RR forming counter, an RI forming counter and an OR gate. The WR, WI forming counter makes initial setting of WR by frame pulse Ff at the time of establishment of frame synchronism from the frame synchronizing circuit basing on clock WCK extracted from a transmission line, and thereafter, pulses are outputted repeatedly at every necessary frequency. In this case, relative phase of periodical pulse WR that designates the head of writing and periodical pulse RR that designates the head of reading is set to make RR positioned at nearly the central time position of adjoining two WR at the time of returning of frame synchronism.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention transfers tarock extracted from a transmission path in a synchronous multiplex converter, a switch, a multimedia multiplexer, a digital cross-connect device, etc. to a clock in the device. This relates to the transmission line end portion.

(Prior Art) Conventionally, a circuit shown in FIG. 3 has been used as a circuit for converting a clock extracted from a transmission line to a clock within a device and matching it to a phase that is easy to process within the device. This circuit is used at the end of a transmission line in a secondary group synchronous multiplex converter, and the clock extracted from the transmission line is multiplied by the clock in the apparatus consisting of a wire mesh synchronizer. In addition, it has a function to match the leading position of the transmission path (humid pulse) with the 8 kHz phase control within the device. Therefore, in this case, the capacity of the elastane ink store is 125 μs (789 bits at the end of the secondary group transmission line).
)Is required. Generally, on a transmission path, frequency phase fluctuations occur due to delay fluctuations in the transmission medium, fluctuations due to the characteristics of the network synchronization device, and the like. It is known that this is approximately within 10 μs. This phase variation is absorbed by the elastane ink store.

In absorbing phase fluctuations in elastics.

Due to fluctuations in the write reset pulse WR indicating the beginning of writing, the phase relationship with the read reset pulse RR indicating the beginning of reading changes, which may cause data to be read twice or data to be missing. Data that is missing is read twice, and the missing data is called a slip. For this reason, as shown in Figure 3,
, the phase difference between WR and RR is compared, and when the phase difference approaches a certain level or more, the delay circuits are completely inserted and removed, thereby forcibly separating the phases of WR and RR into the delay circuit. This is called slip control.

With this circuit, the operating clock becomes the internal clock of the device, and the start positions of the frames of each transmission line are all aligned, that is, 8KHz phase synchronization is performed, so 64
This makes it easier to control arbitrary connections of Kb/s lines.

As mentioned above, when making arbitrary connection changes for 64Kb/s lines, it was necessary to adopt an 8KHz phase, but when making arbitrary connection changes for high-speed lines (
In a device that performs all conversions, it is sufficient to achieve full phase synchronization in accordance with the high-speed line. Now, for example, multiple 4
6.3Mb/s between the next group (100Mb/S) transmission lines
Considering a device that performs arbitrary connection changes of lines, 4
If the next group transmission path frame is m-bit multiplexed on a 6.3 Mb/s line, then 6.3 MHz/m phase synchronization (called block phase synchronization) is sufficient, and if off-tera (8 bit) multiplexed, approximately 0 .8MHz phase synchronization would be sufficient.

FIG. 4 shows an example of information arrangement on an 8-pinto multiplexed quartic group of a 6.3 Mb/s line. If the conventional synchronization method is used as is, the capacity of the elastic store will be approximately 1.25 μs (120 bits), which is the block length. However, with the conventional phase synchronization method, 6.3 MHz/8
If phase synchronization is to be achieved, the capacity of the elastic store is 1.25 μs (approximately 120 bits), whereas the transmission path delay variation is approximately 10 μs (approximately 1000 bits).

In order to ensure the quality of transmission, slips must be avoided. When applying the conventional circuit to 8KHz phase synchronization of the second-order group, one frequency phase fluctuation amount (approximately 60 bits) per elastic capacitance (789 bits)
It) is small, so the probability that a slip will occur first is about 7.6%, which is sufficiently small that there is no problem. ), the above probability becomes 1, and the circuit shown in FIG. 3 can no longer be applied.

(Problem to be Solved by the Invention) Therefore, in a plurality of fourth-order group signals, for example, 6.3
To perform phase synchronization suitable for Mb/s line settings, a phase synchronization method that does not cause slip and has a small elastic capacity is effective, but conventional phase synchronization methods do not satisfy these conditions. Furthermore, if the elastic capacity were to be increased, the size of the 7.-ware would increase and the delay time for information would also increase. Furthermore, no matter how large the elastic capacity is, the occurrence of slip cannot be avoided in the conventional method.

The present invention aims to improve the above problems.

(Another Means to Solve the Problems) A feature of the present invention for achieving the above object is to convert a clock extracted from a signal on a transmission line into a clock within the device, and to convert the clock phase suitable for processing within the device. In the phase synchronization method, a buffer memory using an elastic store for clock conversion is provided, and the relative phase of the synchronous pulse WR that specifies the write start and the periodic pulse RR that specifies the read start is determined by the frame. At the time of synchronization recovery, the two adjacent WRs are set in a phase synchronization method so that the RR is located at the time position of the middle man. This appears as a fluctuation in the readout reset pulse RR, and the above-mentioned slip occurs due to the phase relationship.Therefore, if the period of RR is set to more than twice the maximum amount of frequency phase fluctuation TV that occurs on the transmission path, then the relative If WRf is placed in the middle of RR and RR, no slip will occur.In other words, as shown in Fig. 5, the maximum amount of frequency phase fluctuation kTv that occurs on the transmission path, the formant conversion of the input signal and the When the amount kTr is the amount including the amount required for and the margin, and Tr is selected as an integral multiple of the total block length B of the WR cycle (2XTv+Tr), when the frames are simultaneously restored, RRkTr.

If it is set to 0, the entire slip ratio can be substantially zero.

Now, when using the above symbols TV and Be, the conventional invention considers the case where TV>B, and the slip rate is O.
The difference is that the minimum capacity of the elastic store is given by equation (1).

The eleventh prisoner is a diagram illustrating the first embodiment of the present invention.

It consists of a frame synchronization circuit, WR and WI generation counters, an elastane ink store, a comparison circuit, an RR generation counter, an RI generation counter, and an OR gate. As shown in the timing chart of FIG. 1(B), the WR, WI generation counters are configured to generate frame data when frame synchronization is established from the frame synchronization circuit based on the clock WCK extracted from the transmission path.
(The pulse Ff performs initial settings for WR, and from then on, pulses are repeatedly output for each necessary block frequency.W
The R pulse is input to the elastane ink store, from which input data will be written. Also, WR,
The WI generation counter also generates a write pulse WI required during frame conversion and inputs it to the terminal of the elastic store. The RR generation counter generates WR and WR pulses based on the block pulse RB having a pulse for each block length, the read clock pulse RCK, and the frame pulse Ff (i.e., the initial setting value of WR) at the time of establishing synchronization. It is shown in FIG. 5 in between. During TrO, RR' is set to the initial value, and RR is set to the initial value in (2Tv1T,) period.
Generate a pulse. The RI generation counter generates the elastic store inhibit pulses required for the internal frame format. Further, if the phase difference between RR and WR approaches a certain value or more, the initial setting performed when establishing frame synchronization is performed again.

In the above-mentioned embodiment, the selection and generation were performed based on the read-side phase 1WRt, but since the relative phase relationship between WR and RR may be initialized as shown in FIG. 2, the write-side phase 'tRRk A method of selecting and generating based on a standard is also conceivable. FIG. 2 shows an embodiment in which the writing side phase is completely controlled.

(Effects of the Invention) As explained above, one aspect of the present invention is that when the amount of frequency phase fluctuation TV occurring on the transmission path is large, the amount of information (block) included in the period of phase synchronization suitable for processing of the device is
Using an elastic store with a capacity that is twice as large as 100% and an extra capacity including format conversion, the phase relationship between the read recenthals WR and the write reset pulse RR of the elastic ink store is set at the initial setting (when frame synchronization is established). Since we are controlling the maximum distance, WR and RR
The relative phase of the data becomes normal, which has the advantage that data is read twice in the elastic store, and data loss (slip) often occurs.

[Brief explanation of drawings]

Figure 1 shows the first embodiment of the present invention. 1. Absorbs frequency phase fluctuations Tve that occur on the transmission path without causing slips, and establishes phase synchronization for an amount of information that is smaller than Tv. . FIG. 2 is a second implementation of the present invention. FIG. 3 shows a circuit that absorbs frequency and phase fluctuations occurring on transmission paths and synchronizes the 8 kHz phase of the 8 kHz period frame head position on each transmission path using a clock within the device. FIG. 4 is an example of a fourth-order group signal frame structure in which 15 6.3 Mb/S lines are multiplexed. Figure 5 shows that the amount of frequency phase fluctuation occurring on the transmission path is
The phase relationship between the write reset pulse WR and the read cent pulse RR of the elastic store in which no slip occurs when the amount of information (block amount) within the phase frequency synchronized within the device is larger is shown.

Claims (1)

[Claims] In a phase synchronization method that converts a clock extracted from a signal on a transmission path to a clock in a device and matches the clock phase to a clock phase suitable for processing in the device, a buffer memory using an elastic store for clock conversion is provided. Then, the relative phase of the periodic pulse WR that specifies the beginning of writing and the periodic pulse RR that specifies the beginning of reading is determined such that RR is located at a time position approximately in the center of two adjacent WRs when frame synchronization is restored. A phase synchronization method that is characterized by the following settings.