JPS628697A - Chrominance signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a color signal processing device used in video tape recorders and the like.

Conventional technology Conventionally, the color signal processing method used in consumer video tape recorders converts the frequency of a carrier color signal into a low-pass converted color signal, records it, and converts the frequency again during playback to return it to the carrier color signal. This is a method called color under.

FIG. 6 is a circuit configuration diagram showing an example of a recording system of a color/under one type color signal processing device in a conventional video tape recorder. In the figure, the decoded video signal input from the large sword terminal 1o is filtered through a bandpass filter (hereinafter referred to as BPF).
) 11, the conveyed color signal is taken out. The extracted carrier color signal is adjusted to have a constant burst level in the ACC circuit 12, frequency-converted to a low-pass converted color signal through a balanced modulator 13, and then passed through a low-pass filter (hereinafter referred to as LPF) 14. Unnecessary components generated during balanced modulation are removed at the output terminal 15, and the output signal is output to the output terminal 15.

On the other hand, from the output signal of the human CG circuit 12, a burst signal is taken out by a burst gate circuit 28, and its phase is compared with an output signal of a voltage controlled crystal oscillator (hereinafter referred to as VXO) 31 by a phase comparator 29. Phase error is LPF
30 and controls the VXO 31. In this way VXO
The output signal of 46 is phase-locked to the burst signal of the carrier color signal. Note that 32 indicates a crystal.

The decoded video signal input from the input terminal 1o is separated into a synchronization signal by a synchronization separation circuit 16, and the separated synchronization signal generates an H pulse of one horizontal period (hereinafter referred to as 1H) by an H pulse generator. Created in 17. H
The pulse creates a signal indicating the timing of the burst signal in the burst gate creation circuit 18, and outputs it to the burst gate circuit 28. 320 f a (f H
The output signal of the voltage controlled oscillator (hereinafter referred to as VCO-t) 22 has an oscillation frequency of 1
The frequency is divided by 1/320 in the /320 frequency divider 23, the phase is compared with the H pulse in the phase comparator 20, and the phase error is passed through the LPF 21 to control the VCO 22.

In this way, the oscillation frequency of the VCO 22 is controlled to 320 fH. Further, the output signal of the VCO 22 is frequency-divided by 1/8 in the 1/8 frequency divider 24, and is 40f1
The four-phase signal having an oscillation frequency of 1 and 40 fH is sequentially switched by a signal output from the phase switch pulse circuit 19 and becomes a low frequency carrier wave. In the balanced modulator 26 , the output signal of the VXO 31 is multiplied by the low frequency carrier wave, which passes through the BPF 27 and becomes a carrier for the balanced modulator 13 .

Generally, the output timing of a phase switch pulse circuit is
Taking into consideration the delay time of the BPF 27, etc., the timing is set slightly earlier than the timing of the horizontal synchronization signal.

Below, a part of the conventional H pulse generator and an example of the phase switch pulse circuit shown in FIG. 7 will be explained.

In the same figure, 91 to (h+ is a D flip-flop, 0
1 to G8 are inverters, and Q15 is an RS flip-flop. When the horizontal synchronization signal is input to input terminal 1,
Q9 becomes Hi level, and 1 input from input terminal 2
The reference clock of the oscillation frequency of θofH and Qlo,
Due to Qll and Grtp, G9 becomes the H level during the next one clock after Q9 becomes Hi level. The output of Q9 resets the counter constituted by Q1 to Q a + "1 to G8. After being reset, the counter starts counting the reference clock. Decode C circuit r
/' The 1118th clock is decoded and a pulse is output, and Q9 is reset by the pulse. The reason why the 118th clock is decoded is that it does not accept equivalent pulses or vertical synchronization pulses, but only supports horizontal synchronization signals. In the decode 0 circuit, the 163rd clock is decoded and Q13 is reset. Q13 is then reset when a horizontal synchronizing signal is input and a pulse force is output from Q9. Therefore, the phase switch pulse output terminal has
A pulse is output from the 163rd clock until the pulse is output from Q9. FIG. 8 shows a timing diagram of FIG. 6.

Although the recording system has been described in FIG. 6, the circuit shown in FIG. 7 is necessary not only in the recording system but also in the reproducing system.

Problems to be Solved by the Invention However, in the conventional configuration shown in FIG. 7, if the reproduction signal S/N is poor, especially during special reproduction, and the horizontal synchronization signal is lost, no phase switch pulse is output. , which had the disadvantage of causing color fading and beats on the television screen. Also, if the horizontal synchronization signal is input before the phase switch pulse is output due to the skew that occurs when the tape playback location moves to an adjacent track, the phase switch pulse will not be output and the same as above will occur. It had the following drawbacks.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a color signal processing device that does not cause color fading or beats.

Means for Solving the Problems In order to solve the above problems, the color signal processing device of the present invention includes a counter that counts a reference clock and a counter that decodes the output of the counter to detect when one horizontal period has elapsed. a first decoder that detects the signal and generates a pulse that sets the counter to an initial state; a reset circuit that generates a pulse that sets the counter to an initial state when a horizontal synchronization signal is input; and a decoder that decodes the output of the counter. By doing so, the counter generates a second pulse that switches the phase of the low frequency carrier wave after a predetermined period from the initial state.
The configuration includes a decoder.

Effect of the Invention With the above-described configuration, the present invention decodes from the output of the counter that one horizontal period has elapsed since the counter was reset, and resets the counter again, thereby outputting a phase switch pulse even if the horizontal synchronizing signal is lost. This makes it possible to prevent color fading and beats during special playback.

Examples Below, a color signal processing device according to an example of the present invention will be described.
This will be explained with reference to the drawings. FIG. 1 is a circuit diagram of a color signal processing device mainly including a phase switch pulse circuit according to an embodiment of the present invention.

In the figure, 1 is the input terminal of the decoded synchronization signal, and 2
is a reference clock input terminal, 3 is a reset circuit, 4 is a counter, 5 is a second decoder, 6 is a first decoder, 7
8 represents a phase switch pulse output section, 8 represents an output terminal, and 9 represents a power source. Further, Q1 to Qs21'iD flip-flops, 01 to G8 are inverters, 09 to G11 are AND elements, and G12 + G15 (d OR element).

When a horizontal synchronization signal is input from input terminal 1, Q91d
It becomes Hi (high) level and maintains the H level until a pulse is output from G11. Q+o+(h+ + G
9 constitutes the reset circuit 3, and Q9 changes from the LO level to the H level.
After switching to the i level, a pulse is generated to reset the counter 4 for one clock of the reference clock, and after the reset pulse, the counter 4 starts counting the reference clock. The frequency of the reference clock input from input terminal 2 is 160 fH. The decode C circuit decodes the 118th clock, passes through GH, and resets Q9. Q9 maintains the Lo level until the next horizontal synchronization signal is input. 1 decode circuit.

The decode 5 circuit, Q13, constitutes a second decoder.

The 163rd clock is decoded by the decode 5 circuit and Qls is set. Next, after the counter 4 is reset, the decode 4 circuit decodes the second clock and
Reset 13. Therefore, Qls becomes H level from the 163rd clock until the 2nd clock after the counter is reset once. (The pulse of h3 passes through '45 and is output from output terminal 8. Decode 6 circuit 1d1
Decode the 60th clock. The meaning of the 160th clock is that the reference clock has a frequency of 16ofH.
This indicates that 1H period has passed since the counter was reset. The output pulse of the decode 6 circuit sets G12 to Hi level and resets the counter 4 at the same time. The function of G12 is to indicate that while QH is at Hi level, the counter is not reset by the pulse of the reset circuit 3, but by the output of the decode 6 circuit. During the period when Q10 is at Hi level, G
The gate of N is closed to prevent the pulse of the decode C circuit from reaching 99. Further, G12 is reset by the output pulse of the reset circuit 3. G14ha, 11
It is set at the 8th clock and reset at the 153rd and 2nd clocks. During the period when G14 is at H level, the pulses output from the reset circuit are G10 and G13.
and is output to the output terminal 8. The phase switch pulse output section shown in G13 is particularly meaningful when the horizontal synchronizing signal is input before the 153rd clock, and when the horizontal synchronizing signal is input from the 118th clock to the 163rd clock, Since no pulse is output,
In that case, pulses from 09 are output instead.

2, 3, 4, and 5 are timing diagrams of each part of the circuit shown in FIG. 1. Figure 2 shows the case where the horizontal synchronization signal is input immediately after the lever-16 circuit decodes the 160th clock.1, Figure 3 shows the case where the horizontal synchronization signal is input just before the lever 16 circuit decodes the 160th clock. This is the case. FIG. 4 shows a case where the horizontal synchronizing signal is input before the pulse is output from the second decoder 5. In FIG. 6th
The figure shows a case where the horizontal synchronization signal is lost.

As described above, according to this embodiment, by decoding from the counter output that one horizontal period has passed since the counter was reset, and resetting the counter,
Even if the horizontal synchronization signal is lost, the phase switch pulse can be output, making it possible to prevent color fading and beats during special playback.

Effects of the Invention As described above, the color signal processing device of the present invention detects that one horizontal period has elapsed by using a reference clock as a counter and decoding the output of the counter, and generates a pulse that sets the counter to the initial state. a first decoder that generates a signal, a reset circuit that generates a pulse that initializes the counter when a horizontal synchronization signal is input, and a reset circuit that decodes the output of the counter to change the counter from an initial state to a predetermined state. By providing a second decoder that generates a pulse that switches the phase of the low frequency carrier wave after the period, even if the horizontal synchronization signal is lost during special playback, etc.
It is possible to output a pulse that switches the phase of the low frequency carrier wave, and it is possible to obtain the excellent effect of preventing color fading and beats on the TV screen.

Furthermore, if a pulse is output from the reset circuit to initialize the counter within a predetermined period before the pulse is output from the first decoder, the pulse generated from the output of the reset circuit or the output of the cent circuit is By using a pulse that switches the phase of the low-frequency carrier wave, a pulse is output even if a horizontal synchronization signal is input before the pulse that switches the phase of the low-frequency carrier wave is output, and the color on the TV screen is It is also possible to obtain the effect of preventing erasure and occurrence of beats.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a color signal processing device according to an embodiment of the present invention, FIGS. 2, 3, 4, and 5 are timing diagrams of each part of FIG. 1, and FIG. A block diagram of a recording system of a color signal processing device in a conventional video tape recorder,
Figure 7 is a configuration diagram of a conventional pulse generation circuit, and Figure 8 is a diagram of a conventional pulse generation circuit.
FIG. 1.2...Input terminal, 3...Reset circuit, 4...Counter, 5...Second decoder, 6...First decoder, 7...phase switch pulse output section, 8...output terminal, 9...
··power supply.

Claims (2)

[Claims] (1) A counter that counts a reference clock, a first decoder that detects that one horizontal period has elapsed by decoding the output of the counter, and generates a pulse that sets the counter to an initial state, and horizontal synchronization. a reset circuit that generates a pulse that sets the counter to an initial state when a signal is input; and a reset circuit that decodes the output of the counter to generate a pulse that switches the phase of the low-frequency carrier wave after a predetermined period of time from the initial state. A color signal processing device comprising a second decoder that generates a color signal. (2) The pulse that switches the phase of the low-frequency carrier wave is output from the reset circuit when a pulse that initializes the counter is output from the reset circuit within a predetermined period before the pulse is output from the first decoder. The color signal processing device according to claim 1, wherein the output pulse is a pulse generated from the output of the reset circuit.