JPS628775B2 - - Google Patents
Info
- Publication number
- JPS628775B2 JPS628775B2 JP10142777A JP10142777A JPS628775B2 JP S628775 B2 JPS628775 B2 JP S628775B2 JP 10142777 A JP10142777 A JP 10142777A JP 10142777 A JP10142777 A JP 10142777A JP S628775 B2 JPS628775 B2 JP S628775B2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- shutter
- operational amplifier
- output
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Shutter-Related Mechanisms (AREA)
- Electronic Switches (AREA)
- Exposure Control For Cameras (AREA)
Description
【発明の詳細な説明】
本発明は高速シヤツタ作動時にも正確な動作を
行なう電子シヤツタにおける対数伸長積分回路に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logarithmic expansion and integration circuit in an electronic shutter that operates accurately even during high-speed shutter operation.
本発明者が先に提案した特願昭52−85752号明
細書に示すような第１図図示の電子シヤツタにお
ける対数伸長積分回路は単一電源使用のため有用
である。即ち写真機の測光部１、演算部２の出力
がシヤツタ作動用開閉器SW0を介して直列接続さ
れた抵抗素子R1乃至R4を経て演算増幅器３の反
転入力端子（−）に印加されている。積分動作用
容量素子Ｃによつて対数伸張された電圧が比較器
４において比較電圧Vrと比較される。対数伸張
された電圧がVr以下となつた時電磁石５の励磁
が解除され、シヤツタの後幕が走行しシヤツタ秒
時が決定される。この装置においてはシヤツタ動
作用開閉器SW0をONとした瞬間、測光部１、演
算部２の出力は殆んど抵抗素子R1のみに印加さ
れ、通常の明かるさ以下の被写体では問題になら
ないが、特に明かるい被写体を測光したとき（高
速シヤツタ動作を必要とするとき）大電流が開閉
器SW0を通過する。 The logarithmic expansion and integration circuit in the electronic shutter shown in FIG. 1, as previously proposed by the present inventor in Japanese Patent Application No. 52-85752, is useful because it uses a single power source. That is, the outputs of the photometry section 1 and calculation section 2 of the camera are applied to the inverting input terminal (-) of the operational amplifier 3 via the shutter operating switch SW 0 and the resistive elements R 1 to R 4 connected in series. ing. The voltage logarithmically expanded by the integral capacitive element C is compared with the comparison voltage Vr in the comparator 4. When the logarithmically expanded voltage becomes equal to or lower than Vr, the excitation of the electromagnet 5 is released, the rear curtain of the shutter runs, and the shutter time is determined. In this device, the moment the shutter operation switch SW 0 is turned on, the outputs of the photometer 1 and the calculation section 2 are applied almost only to the resistor R 1 , which causes a problem when the subject is photographed under normal brightness. However, especially when metering a bright subject (when high-speed shutter operation is required), a large current passes through the switch SW 0 .
そのため演算部２の出力インピーダンスが十分
小さくなければ大電流のため、演算部出力電圧が
所定の電圧を出力する積りであつても、電圧低下
を起し高速シヤツタ動作ができず、シヤツタ秒時
が所定値から長い方に変動する欠点がある。また
開閉器SW0を機械的な開閉器でなく電子開閉器特
にFET使用の開閉器として構成すると開閉回路
両端の電圧降下は前記大電流を流すと無視できず
シヤツタ秒時に影響を与える。開閉器SW0を通常
のトランジスタで構成すると電圧降下は問題が少
ない反面ベース電流を無視することができず、何
れにしても電子開閉器の開閉制御に問題が多くな
り、高速シヤツタが要求される場合十分な機能を
果たすことが困難となる場合がある。 Therefore, if the output impedance of the calculation section 2 is not sufficiently small, the current will be large, and even if the calculation section output voltage is a product that outputs a predetermined voltage, the voltage will drop and high-speed shutter operation will not be possible, resulting in a slow shutter speed. There is a drawback that it fluctuates longer than a predetermined value. Furthermore, if the switch SW 0 is configured not as a mechanical switch but as an electronic switch, particularly a switch using an FET, the voltage drop across the switching circuit cannot be ignored when the large current is passed, and affects the shutter speed. If the switch SW 0 is configured with a normal transistor, the voltage drop will be less of a problem, but the base current cannot be ignored, and in any case, there will be many problems with the switching control of the electronic switch, and a high-speed shutter will be required. In some cases, it may be difficult to perform a sufficient function.
本発明は高速シヤツタ作動時にも演算部出力イ
ンピーダンス及び開閉器のインピーダンスにより
シヤツタ速度に影響を与えず正確な動作の可能な
電子シヤツタ駆動装置を提供することを目的とす
る。 SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic shutter drive device that can operate accurately even during high-speed shutter operation without affecting the shutter speed using the output impedance of the calculation section and the impedance of the switch.
以下図面に示す本発明の実施例について詳細に
説明する。第２図において第１図と同一符号は同
一のものを示し、シヤツタ動作開閉器SW0は第２
図において抵抗素子R1と基準電位この場合は接
地との間に接続される。第１開閉器SW1は演算部
２の出力端子と演算増幅器３の反転入力端子
（−）間に接続し、第２開閉器SW2は演算増幅器
３の出力端子と基準電位この場合接地との間に接
続される。 Embodiments of the present invention shown in the drawings will be described in detail below. In Fig. 2, the same symbols as in Fig. 1 indicate the same parts, and the shutter operation switch SW 0 is the second
In the figure, a resistive element R1 is connected between a reference potential, in this case ground. The first switch SW 1 is connected between the output terminal of the calculation section 2 and the inverting input terminal (-) of the operational amplifier 3, and the second switch SW 2 is connected between the output terminal of the operational amplifier 3 and the reference potential, in this case, ground. connected between.
測光部１において被写体の明かるさを測り演算
部２においてフイルムの感度ASA値と絞り値と
により定められたシヤツタ速度に対応する電圧が
演算増幅器３の反転入力端子（−）に印加された
状態とし、その時開閉器SW0はOFF、開閉器
SW1，SW2は共にONとしておく。演算増幅器３
の出力端子にはトランジスタTr11を挿入しそのエ
ミツタ電極に積分動作用容量素子Ｃが持続されて
いて、エミツタ電極が接地電位となつている。容
量素子Ｃの他端は演算増幅器３の反転入力端子
（−）のためその側は演算部２の出力電位と等し
く、したがつて容量素子Ｃは演算部２の出力電位
によつて充電されていることとなる。比較器４の
出力端子はこの時電圧が生じ電磁石５を励磁し、
シヤツタ後膜を保持している。シヤツタ動作のた
めシヤツタ先膜を走行させるよう操作するとシヤ
ツタ動作開閉器SW0をONとし、SW1，SW2は
OFFとされる。演算増幅器３は積分動作を開始
しその出力端子電圧は上昇し始める。積分動作は
換言すれば演算部２の出力について対数伸張して
いることである。演算増幅器３の出力電位が比較
器４の比較電位Vrより高くなると電磁石５の励
磁が解かれ、保持されていた後膜が走行し所定の
シヤツタ秒時が得られる。 The photometer 1 measures the brightness of the subject, and the calculation unit 2 applies a voltage corresponding to the shutter speed determined by the film's sensitivity ASA value and aperture value to the inverting input terminal (-) of the operational amplifier 3. At that time, switch SW 0 is OFF, switch
Leave SW 1 and SW 2 both ON. Operational amplifier 3
A transistor Tr11 is inserted into the output terminal of the transistor Tr11, and a capacitive element C for integral operation is connected to the emitter electrode of the transistor Tr11, and the emitter electrode is at ground potential. Since the other end of the capacitive element C is the inverting input terminal (-) of the operational amplifier 3, that side is equal to the output potential of the arithmetic unit 2, and therefore the capacitive element C is charged by the output potential of the arithmetic unit 2. There will be. At this time, a voltage is generated at the output terminal of the comparator 4, which excites the electromagnet 5.
Retains membrane after shutter. When the shutter tip membrane is operated for shutter operation, the shutter operation switch SW 0 is turned on, and SW 1 and SW 2 are turned on.
It is considered OFF. Operational amplifier 3 starts integrating and its output terminal voltage begins to rise. In other words, the integral operation is logarithmic expansion of the output of the calculation section 2. When the output potential of the operational amplifier 3 becomes higher than the comparison potential Vr of the comparator 4, the excitation of the electromagnet 5 is released and the held rear membrane runs to obtain a predetermined shutter time.
以上の動作において開閉器SW0，SW1，SW2は
機械的なものとして説明したが、シヤツタの高速
動作の場合は開閉動作を同期させることが困難と
なり、また信頼性に欠けるため電子的開閉器を使
用することが好都合である。第３図は開閉器
SW0，SW1，SW2として半導体素子を使用する場
合を示している。即ち開閉器SW0としてはトラン
ジスタTr0を使用し、開閉器SW1としてＮチヤン
ネルFETのTr1、同SW2として通常のトランジス
タTr2を使用し、これらを同時に開閉するための
開閉器としてSWaを用いる。トランジスタTr0の
開閉は、ベース電極と接地間に接続された開閉器
SWaをON、OFFすることにより行ない、また
SW1相当のFETと、SW2相当のTr2のON、OFF
は位相反転トランジスタTr3をON、OFFするこ
とにより行なつている。このように構成すること
により、シヤツタ先膜の走行開始時点の信号を開
閉器SWaを開くことによつて取出すだけで、
SW0，SW1，SW2の３個の開閉器の同時性が得ら
れて好都合であり、接点数も少なくなり、また開
閉器SWaの開閉動作時チヤタリング現象による
悪影響がなく信頼性の高い回路となる。 In the above operation, the switches SW 0 , SW 1 , and SW 2 have been explained as mechanical switches, but in the case of high-speed shutter operation, it is difficult to synchronize the opening and closing operations, and they are unreliable, so electronic switching is used. It is convenient to use a container. Figure 3 shows the switch
The case where semiconductor elements are used as SW 0 , SW 1 , and SW 2 is shown. That is, the transistor Tr 0 is used as the switch SW 0 , the N-channel FET Tr 1 is used as the switch SW 1 , the normal transistor Tr 2 is used as the switch SW 2 , and SWa is used as the switch to open and close these at the same time. Use. The transistor Tr 0 is opened and closed by a switch connected between the base electrode and ground.
This is done by turning SWa ON and OFF, and
ON/OFF of FET equivalent to SW 1 and Tr 2 equivalent to SW 2
This is performed by turning on and off the phase inversion transistor Tr3 . With this configuration, the signal at the start of travel of the shutter tip membrane can be retrieved simply by opening the switch SWa.
It is convenient because the three switches SW 0 , SW 1 , and SW 2 can operate simultaneously, and the number of contacts is reduced. Also, there is no adverse effect due to the chattering phenomenon during the opening/closing operation of the switch SWa, resulting in a highly reliable circuit. becomes.
なおFETTr1としてＰチヤンネルFETを使用
し、第３図に示す開閉器SWaのｈ点電圧により
制御することもできる。唯FETゲートのカツト
オフ電圧に留意する必要がある。またTr1として
演算部２の出力インピーダンスがあまり高くない
ときは、バイポーラトランジスタを使用すること
ができる。 Note that it is also possible to use a P-channel FET as FETTr 1 and control it by the h-point voltage of the switch SWa shown in FIG. The only thing you need to pay attention to is the cutoff voltage of the FET gate. Further, a bipolar transistor can be used as Tr 1 when the output impedance of the calculation section 2 is not very high.
このようにして本発明によるとシヤツタ先幕を
走行させるため、シヤツタ動作用開閉器SW0を
ONとしたとき演算部の出力は演算増幅器の入力
端子に接続されているのみであるから、従来回路
のように高速シヤツタ動作を行なうため、演算部
出力インピーダンスを十分小とすることを必要と
するような制限事項が生じない。したがつて演算
部を構成する回路の設計が簡易になる。また前記
シヤツタ動作用開閉器に演算増幅器の積分動作中
大電流が流れる場合、同開閉器としてトランジス
タを使用することができそのときトランジスタ
ON時の飽和電圧が低く片側の電圧レベルが接地
電位に固定されているので、ベース電極の制御入
力に制限が少ない。そのため高速シヤツタ動作の
場合にも正確な動作が得られる。 In this way, according to the present invention, in order to run the front shutter curtain, the shutter operating switch SW 0 is activated.
When turned ON, the output of the calculation section is only connected to the input terminal of the operational amplifier, so in order to perform high-speed shutter operation like the conventional circuit, the output impedance of the calculation section must be made sufficiently small. There are no such restrictions. Therefore, the design of the circuit constituting the arithmetic unit is simplified. In addition, if a large current flows through the shutter operation switch during the integral operation of the operational amplifier, a transistor can be used as the switch.
Since the saturation voltage when ON is low and the voltage level on one side is fixed at ground potential, there are few restrictions on control input to the base electrode. Therefore, accurate operation can be obtained even in the case of high-speed shutter operation.
第１図は先に提案された電子シヤツタにおける
対数伸長積分回路の構成図、第２図は本発明実施
例を示す構成図、第３図は第２図中の開閉器とし
て半導体素子を使用する場合の構成図である。
１……測光部、２……演算部、３……演算増幅
器、R1，R2，R3，R4……直列接続抵抗素子、
C1，C2，C3……容量素子、SW1……第１開閉
器、SW2……第２開閉器。
Fig. 1 is a block diagram of a logarithmic expansion/integration circuit in an electronic shutter previously proposed, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 uses a semiconductor element as the switch in Fig. 2. FIG. DESCRIPTION OF SYMBOLS 1...Photometry part, 2...Arithmetic part, 3...Operation amplifier, R1 , R2 , R3 , R4 ...Series connected resistance element,
C 1 , C 2 , C 3 ... Capacitive element, SW 1 ... First switch, SW 2 ... Second switch.
Claims (1)
ヤツタ動作用開閉器を介して接続された複数の直
列接続抵抗素子と、該抵抗素子の接続点と反転入
力端子間に接続された複数の容量素子と、対数圧
縮された測光出力を得る測光演算部の出力端子と
前記演算増幅器反転入力端子間に接続された第１
開閉器と、前記演算増幅器出力端子と基準電位間
に接続された第２開閉器と、演算増幅器出力を非
反転入力端子へ帰還する帰還路中に設けられた積
分動作用容量素子とを具備し、演算増幅器の非反
転入力端子には前記測光演算部出力が印加される
構成であつて、 写真機シヤツタ先幕走行開始前にはシヤツタ動
作用開閉器をオフ、第１開閉器・第２開閉器を共
にオンとし、 写真機シヤツタ動作開始時にシヤツタ動作用開
閉器をオンとすると同時に、前記第１・第２開閉
器をオフとし、シヤツタ始動時より演算増幅器出
力電圧が所定値に達するまでの時間を測光出力に
対して指数関数の関係を有するように構成したこ
とを 特徴とする電子シヤツタにおける対数伸長積分回
路。[Claims] 1. A plurality of series-connected resistance elements connected between the inverting input terminal of an operational amplifier and a reference potential via a shutter operation switch, and a connection between the connection point of the resistance elements and the inverting input terminal. a plurality of capacitive elements, and a first one connected between the output terminal of the photometric calculation unit that obtains the logarithmically compressed photometric output and the inverting input terminal of the operational amplifier.
A switch, a second switch connected between the operational amplifier output terminal and a reference potential, and an integral operation capacitive element provided in a feedback path that returns the operational amplifier output to the non-inverting input terminal. , the output of the photometry calculation section is applied to the non-inverting input terminal of the operational amplifier, and before the front curtain of the camera shutter starts running, the shutter operation switch is turned off, and the first switch and second switch are turned off. When the camera shutter starts operating, turn on the shutter operation switch and turn off the first and second switches at the same time. 1. A logarithmic expansion and integration circuit for an electronic shutter, characterized in that the time is configured to have an exponential relationship with the photometric output.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10142777A JPS5434819A (en) | 1977-08-24 | 1977-08-24 | Electronic shutter driving device by use of logarithm extension circuit |
| US05/923,903 US4213683A (en) | 1977-07-18 | 1978-07-12 | Electronic shutter driving device for camera |
| DE2831520A DE2831520C3 (en) | 1977-07-18 | 1978-07-18 | Electronic shutter control device for a camera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10142777A JPS5434819A (en) | 1977-08-24 | 1977-08-24 | Electronic shutter driving device by use of logarithm extension circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5434819A JPS5434819A (en) | 1979-03-14 |
| JPS628775B2 true JPS628775B2 (en) | 1987-02-24 |
Family
ID=14300398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10142777A Granted JPS5434819A (en) | 1977-07-18 | 1977-08-24 | Electronic shutter driving device by use of logarithm extension circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5434819A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03212081A (en) * | 1990-01-17 | 1991-09-17 | Sharp Corp | Magnetic recording and reproducing device |
-
1977
- 1977-08-24 JP JP10142777A patent/JPS5434819A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03212081A (en) * | 1990-01-17 | 1991-09-17 | Sharp Corp | Magnetic recording and reproducing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5434819A (en) | 1979-03-14 |
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