JPS62877A - Test facilitating logic circuit - Google Patents

Abstract

PURPOSE:To obtain a test facilitating circuit which has a small wiring area by utilizing a data bus which connects with the majority of registers as a scan bus. CONSTITUTION:In normal operation, the scan output control terminal 19 of an FF is held at 0 to put a control circuit 23 in an HI (high impedance) state and 0 is inputted to the control signal terminal 27 of a NOR gate 25 to control the output signal of a control circuit 23 with a signal 26. Consequently, only a FF 22 is connected to a common bus for output. Other FFs which need not be connected are controlled only by applying 1 as the signal 26 of the gate 25 at any time. When a test is made, a terminal 27 is held at 1 and a terminal 19 is held at 0 firstly to send an output HI from registers 6-8 to the common bus, a test clock 16 is used for a register 6, 7, or 8 specified through a terminal 17, and test data is scanned in from a common bus 2' through a terminal 14. Then, the terminal 27 is held at 0 and the terminal 19 is held at 0 to perform normal operation. Lastly, 1 is inputted to the terminal 27 and the signal of a register whose terminal 19 is held at 1 is scanned out through the common bus 2' in synchronization with the clock 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to testability circuits using scan path techniques.

[Technical background of the invention and its problems]

recent years. As LSIs become more highly integrated, the demand for testable circuits is increasing. Particularly for circuits including sequential circuits, the increase in test patterns is likely to result in an increase in test costs.

In order to reduce this test cost, one typical test-facilitating circuit is one that has a scan input terminal and the supplied system clock can be controlled externally, and a system clock that uses a separate scan clock. State memory circuit (flip-flop...F/P
This test facilitation circuit makes it possible to use a test control signal to designate the register to be scan input or scan output at the time of scan input or scan output by forming a groove in each register using There is.

The above-mentioned conventional technology will be explained using FIGS. 3 and 4. FIG. 3 shows that a combinational circuit section l and registers 6 to 8 are mounted on a chip. Figure 4 shows details of that one register. The register consists of an F/F 22 and a control circuit 23.

F/F22 that constitutes the register is system clock 1
5, the data from the combinational circuit section 1 is read from the data input terminal 13, and when the scan input control terminal 17 of the F/F is 11", the data is read from the scan input terminal 14 in synchronization with the test clock 16. It is a state memory circuit that reads data. The ll control circuit 23 outputs high impedance when the scan output control terminal 19 is @0", and the output of the F/F does not affect the scan path 12 and is "1'', the contents stored in the F/F are output to the output signal line 21.

Therefore, it is possible to selectively output the F/F.

Explain the haiku composition during the test. First, scan the test data placed on the scan path 12 on the input side f4 terminal 1.
A scan input is made from the terminal 14 using the test clock 16 to the register 6.7 or 8 designated by the 'l' or '0' input to the register 7.

Next, the system clock 15 is operated, test data is output to the combinational logic circuit section 1, and the circuit operation result is read into the F/F from the data input terminal 13.

Finally, the signal of the register designated by the @1'' input to the scan output control terminal 19 is scanned out using the scan path 12, and its value is compared with the expected value.

Since such a testability circuit sends multi-bit information to the scan path 12, the scan speed is faster than the conventional testability circuit that uses a single scanpath.
Furthermore, by being able to specify registers for scan input and scan output using control signals, there is an advantage that only the values of the registers to be compared can be output.

However, since the scan path is used, there is a problem in that the number of wiring lines increases significantly and the wiring area becomes large.

[Purpose of the invention]

The present invention is an attempt to improve the above-mentioned drawbacks of the conventional circuit, and an object of the present invention is to provide a test-facilitated circuit with a small area for failure.

[Summary of the invention]

During testing, a group of signal lines that are trusted to input signals from the outside to the internal F/F and to output signals from the internal F/F to the outside are called a scan path.

The testability circuit according to the present invention is characterized in that the scan path and the signal line of the combinational logic circuit section used in the normal mode are shared by the same signal line.

〔Effect of the invention〕

A logic circuit inherently has a data bus connected to most registers, and by using this as a scan path, the number of wires and the wiring area can be reduced.

[Embodiment of the Invention] FIG. 1 is an overall view of a chip according to an embodiment of the invention, and FIG. 2 is an enlarged view focusing on one register.

As shown in FIG. 11, the data bus 2- of the combinational logic circuit section 1 also serves as a scan path.

The details of the configuration will be explained below along with the operation.

Normal operation %F/F scan output side 89 child 19 to 10
1, the control circuit 23 is set to high impedance, and
@O'' is input to the control signal terminal 27 of the NOR gate 25, so that the output state of the 11 control circuit 23' can be controlled by the control signal 26 generated by the decoder. Construct F/',
When outputting the F/F 22 to the shared bus, it is possible to output only the F/F 22 designated by the decoder to the shared bus. In addition, for F/Fs that do not need to output to the shared bus during normal operation, the control signal 2 of the NOR gate 25
6 should be always set to 01''.

During testing: ■First, set signal terminal 27 to “1”.

19 to "O" so that the output of all registers 6.7.8 to the shared bus becomes high impedance, and connect the test clock to the register 6, 7, or 8 specified by the input control terminal 17. 16 is used to manually scan test data from the common bus 2' via the scan input terminal 14.Next, the signal terminal 27 is set to "0" and 19 is set to "O" to perform the normal operation described above.

■Finally, @1'' is input to the signal terminal 27, and the register signal whose scan output control terminal 19 is set to 11'' is sent to the test clock 16 at the same time as the shared bus 2'.

, scan output via .

As described above, according to the present invention, it is possible to reduce the wiring area by sharing one normal signal @ for scanning.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a testability circuit according to the present invention. FIGS. 3 and 4 are block diagrams and circuit diagrams of a testability circuit using a conventional random access scan canvas. In the figure, 1...Combination circuit section, 2...Data bus, 3-5
...Signal line group between register and combinational circuit section, 6 to 8
...Register, 9-11...Signal line group between register and scan path, 12...Scan path, 13...F
/P data input terminal, 14...F7F scan input terminal, 15...F/F' system clock, 16
...II'/F test clock, 17...F/F
18...F/F output terminal, 19...F/F scan output control terminal, 20...
・F/F output signal line, 21... Control circuit output signal line, 22... F/P, 23.23'... Sub-leg circuit,
24...Combination circuit, 25...NOR gate, 2
6... Output side leg signal from register to data bus, 2
7... Control signal during testing, 2'... Shared bus for scan canvas and data bus 3-4z51... Signal line group between shared path and registers. Agent Attorney Chika Nori 'II Right C and 1 other person] Figure 3 Figure 4

Claims (3)

[Claims] (1) In a testability circuit characterized by being able to output and input the stored contents of the state storage circuit to the outside using a scanning signal line, the scanning signal line and the signal line used in normal operation are connected to each other. A testable logic circuit characterized by sharing the same signal line. (2) The testability logic circuit according to claim 1, wherein a data line is used as the same signal. (3) Add a control circuit to the signal line that connects the sequential circuit section and the combinational circuit section and that is used in the normal mode, and make the signal from the signal line to the combinational circuit section high impedance during the test mode. 3. The testability logic circuit according to claim 1 or 2, which has a feature that enables testability.