JPH09145802A - Pattern generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multiplication pattern by returning the output of plural ALU circuits to which the output of a main register is input to the main register through a select circuit, and retiming the same through another select circuit controlled by a sequence circuit. SOLUTION: A system clock of a timing generating part 7 is divided into three parts by a frequency divider 8 to be fed to a main register 1, auxiliary registers 13, 23, 33, and retiming circuits 41, 42, 43. In synchronization with the above, signals are sent from the register 1 to ALU circuits 12, 22, 32, and the arithmetic results 12A. 22A, 32A are sen to circuits 41, 42, 43 for retiming in synchronization with a dividing clock and sequentially output from an output register 4 with delay of one period of a dividing clock by a select circuit 2 controlled by a sequence circuit 6. The arithmetic results 12A, 22A, 32a are simultaneously passed through the select circuit 2 and feedbacked to the register 1. In this arrangement, it is possible to generate a test pattern at high speed with a small number of parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generation circuit, and more particularly to a test pattern generation technique in a pattern generation circuit used in an IC tester for testing a memory IC or the like.

[0002]

2. Description of the Related Art In recent years, memory ICs have a very short cycle time (access time) of 66 MHz to 130 MHz in order to keep up with high speed / high functionality of microprocessors and the like. Therefore, it is required to generate a faster test pattern in an IC tester that measures this type of IC. And in order to generate such a high-speed test pattern,
A pattern generation circuit in the IC tester that can perform high-speed calculation is required.

A pattern generation circuit used in an IC tester for measuring a memory IC or the like is generally called an algorithmic pattern generation circuit (hereinafter referred to as an ALPG circuit). In this ALPG circuit, a test pattern (scan, march,
Gallop etc.) can be easily generated. In this case, in order to easily generate such a pattern, a dedicated arithmetic circuit (Arithmetic)
Logic Unit: Hereinafter referred to as "ALU circuit". ) Is required.

Next, FIG. 5 shows a block diagram of a conventional example of a pattern generation circuit for generating a high speed pattern.
In FIG. 5, 11 is a main register, 12 is an ALU circuit, and 13
Is an auxiliary register, 14 is a timing generation circuit, 15 is a sequence controller, and 16 is a control memory. Note that FIG. 5 shows an example of an interleave circuit in which a plurality of ALPG circuits 18, 28, 38 are arranged in parallel and output signals are sequentially selected.

Since the ALPG circuits 18, 28 and 38 have the same structure, only the ALPG circuit 18 will be described. In FIG. 5, the main register 11 is a memory IC.
Memorize the pattern added to the device such as. The auxiliary register 13 is a calculated value for the main register 11 and operates at the same clock as the main register 11. A
The LU circuit 12 executes four arithmetic operations on the output value of the main register 11 and the output value of the auxiliary register 13.

The timing generation circuit 14 generates a system timing clock for the ALPG circuit. The sequence control unit 15 decodes the execution order (execution address) of the program according to the program instruction, and outputs it to the control memory 16 in which the operation instruction and the like are stored as the execution address. The control memory 16 is
Operation control instruction 15 output from the sequence control unit 15
A (Operation control instruction 25 in the case of ALPG circuits 28 and 38)
A, 35A) signal 16A (ALPG circuit 2) designating the operation item of ALU circuit 12 according to the output address
In the case of 8 and 38, signals 26A and 36A) are output. A
The LU circuit 12 outputs the operation output signal 12A (A
In the case of the LPG circuits 28 and 38, the signals 22A and 32A) are output to the main register 11.

Next, the operation of the pattern generating circuit of FIG. 5 will be described with reference to the time chart of FIG. Where AL
System clock 14A of the PG circuits 18, 28, 38,
24A and 34A are programmed so that they occur at a rate of one by one. Then, these system clocks 14A, 24A, 34A are input to the sequential circuit 61, and the system clock 61A is calculated from the logical sum of these signals.
Is created. Further, the sequential circuit 61 includes the main register 1
For the selection circuit 5 that selects the output of 1, 21, and 31,
Selection control signal 61B in synchronization with system clock 61A
Is output. In accordance with the selection signal 61B, the sequential outputs from the main registers 11, 21, 31 are retimed by the output register 4 and output from the output register 4.

[0008]

However, in the conventional pattern generation circuit, a plurality of ALPG circuits are used in parallel in the operation of the address register, and it is necessary to have an ALU circuit and a register for each interleave. , The number of parts increases. There is also a problem that signals cannot be exchanged between different main registers.

An object of the present invention is to provide a pattern generator capable of exchanging signals between main registers and reducing the number of parts.

[0010]

To achieve this object, a pattern generating circuit according to the first aspect of the present invention includes a timing generating circuit for generating a system clock and a frequency dividing clock obtained by dividing the system clock into a plurality of frequencies. A frequency dividing circuit for outputting, a sequence control circuit for controlling a predetermined program instruction, a control memory for storing the program instruction, a main register for storing pattern data, and an auxiliary for storing operation data for the output of the main register. A register, a plurality of ALU circuits for calculating the output data of the main register and the output data of the auxiliary register, and a first selection for selecting one of the outputs of the plurality of ALU circuits and outputting it to the main register. And a circuit. Further, further, the plurality of ALs
A retiming circuit for retiming the output of the U circuit in synchronization with the divided clock, a second selection circuit for serially rearranging the output from the retiming circuit, and an output of the second selection circuit An output register for retiming with a system clock and a sequential circuit for controlling the second selection circuit may be further provided.

The pattern generating circuit of the second invention is
A timing generating circuit for generating a system clock, a frequency dividing circuit for dividing the system clock into a plurality of frequencies and outputting a frequency-divided clock, a sequence control circuit for controlling a predetermined program instruction, and a control for storing the program instruction. A memory, a plurality of main registers for storing pattern data, an auxiliary register for storing operation data for the outputs of the plurality of main registers, and an operation of the output data of the plurality of main registers and the output data of the auxiliary register. A plurality of ALU circuits and one of the outputs of the plurality of main registers are selected to select the plurality of ALU circuits.
A first selection circuit for outputting to the circuit. Furthermore, a second selection circuit that serially rearranges outputs from the plurality of main registers, and the second selection circuit.
The configuration may further include an output register for retiming the output of the selection circuit in accordance with the system clock, and a sequential circuit for controlling the second selection circuit.

That is, in the first aspect of the invention, the output of one main register is input to a plurality of ALU circuits, and the output of a plurality of ALU circuits is input to this main register by the first selection circuit. Further, in the second invention, the same number of main registers as the plurality of ALU circuits are provided, and the output of the main register is selected and input to each ALU circuit by the first selection circuit. And
The output of each ALU circuit or main register is selected by the second selection circuit controlled by the output of the sequential circuit, retimed by the output register, and multiplied by the number (parallel number) of ALU circuits. A pattern is generated.

In the pattern generating circuit of the present invention having the above configuration, a divided clock obtained by dividing the system clock by the parallel number is used, and the same register output is input to a plurality of ALU circuits. Alternatively, since the outputs of the plurality of main registers are selected and input to the plurality of ALU circuits by the first selection circuit, it is possible to exchange signals between the main registers. Further, since the output is selected and input by the first selection circuit, the circuit configuration can be simplified and the number of parts constituting the pattern generation circuit can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, FIG. 1 shows a pattern generation circuit according to an embodiment of the first invention. This pattern generation circuit shows a configuration example of three parallel interleaves, and includes a timing generation unit 7 that generates a system timing, a frequency dividing circuit 8 that divides the system clock by the number of parallel stages, and a frequency dividing unit. It also comprises a sequence control unit 9 which operates with a clock, a control memory 10, and a main register 1 which also operates with a divided clock.

Auxiliary registers 13 and 2 arranged in parallel with the output signal 1A of the main register 1 by the number of parallel stages.
3, 33, and ALU circuits 12, 22, 3 that operate according to a program stored in the control memory 10.
2 and 2 are arranged in parallel. In addition, the operation output signals 12A, 22A, 3 of the ALU circuits 12, 22, 32,
The selection circuit 2 for feeding back 2A to the main register 1 to select and output it, and the above-mentioned operation output signal 12
It has retiming circuits 41, 42, and 43 composed of flip-flops for retiming A, 22A, and 32A in synchronization with the divided clock 8A.

Also, these retiming circuits 41, 4
A selection circuit 5 for serially outputting 2 and 43 in synchronization with the system clock, an output register 4 including a flip-flop for retiming the output of the selection circuit 5, and a selection signal and a latch for the selection circuit 5 and the output register 4. It comprises a sequential circuit 6 for generating a clock (system clock).

Next, FIG. 3 shows a timing chart of the pattern generating circuit of FIG. Here, the timing generator 7
The system clock 7A is periodically generated. Then, the system clock is divided into three by the frequency dividing circuit 8, and the main register 1 and the auxiliary register 1 are used as the divided clocks.
2, 23, 33 and retiming circuits 41, 42,
43 is input. Signals are sent from the main register 1 to the ALU circuits 12, 22, 32 in synchronization with this clock, and the calculation results 12A, 22A, 32A are output from the ALU circuits 12, 22, 32, respectively.

Each ALU is divided by one cycle of the divided clock.
Since the operation results of the circuits 12, 22, 32 are sequentially output, the instruction is output from the sequential circuit 6 as the selection signal 6A. Then, the selection circuit output 5A is output in the order of selection, and an output signal is obtained in synchronization with the system clock. The output signal is delayed from the output of the selection circuit 2 by one cycle of the system clock.

In the embodiment shown in FIG. 1, the ALPG circuit using three ALU circuits is taken as an example.
The number of LU circuits is not limited to this, and any number can be used as long as it is two or more.

In order to increase the number of test pattern outputs, it is necessary to increase the number of ALU circuits in the ALPG circuit. In the conventional structure, the same number of main registers as ALU circuits are required. In the configuration of the first invention, only one main register is required for a plurality of ALU circuits, and there is an advantage that the number of parts can be reduced even at the same address speed.

Next, FIG. 2 shows an embodiment of the pattern generating circuit of the embodiment of the second invention. In FIG. 2, 1
Reference numerals 2, 22, and 32 are ALU circuits that perform arithmetic processing. These outputs are input to the main registers 11, 21, and 31 which correspond to them one-to-one. ALU circuits 12, 2
The sequence control circuit 9 executes the calculation items 2 and 32 according to the program (calculation item) stored in the designated program address.

The output signals of the main registers 11, 21, 31 are fed back to the three ALU circuits 12, 22, 32 and selected by the selection circuits 17, 27, 37. In this way, the ALU circuits 12, 2
2, 32, the main registers 11, 21, 31 and the selection circuits 17, 27, 37 are connected in a loop,
The ALPG circuit described above is configured. In the configuration of FIG. 2 as described above, although the number of main registers does not change, it is possible to perform calculations using the outputs of the main registers of each other, so that there is less limitation in creating a program for pattern generation.

Next, a timing chart of the pattern generating circuit of FIG. 2 is shown in FIG. Here, the movement of each part of the pattern generation circuit of FIG. 2 is basically the same as that shown in FIG. That is, the timing generator 7 periodically generates the system clock 7A. Further, the system clock is divided into three by the frequency dividing circuit 8, and the main registers 11, 21, 31 and the auxiliary registers 13, 2 are used as the divided clocks.
3, 33, and the output register 4, respectively. Also, in synchronization with the divided clock, each ALU circuit 12, 22,
The calculation result of 32 is input to the selection circuits 17, 27 and 37 through the main registers 11, 21 and 31. And
The sequential circuit 6 issues a selection signal 6A for instructing to sequentially output the calculation result, and the selection circuits 17, 27 and 37 output signals in response to the selection signal 6A. Further, in synchronization with the divided clock, the output signal 4A is output from the output register 4.

[0024]

According to the pattern generating circuit of the present invention,
Since the number of parts can be reduced, the circuit configuration can be simplified, the number of parts that make up the pattern generation circuit can be reduced, and a test pattern can be generated at high speed with a smaller number of parts than before. it can. Also, since signals can be exchanged between the main registers, the restriction on the program creation for pattern generation is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a pattern generating circuit according to the first invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a pattern generating circuit according to the second invention.

3 is a time chart of the pattern generation circuit of FIG.

FIG. 4 is a time chart of the pattern generation circuit of FIG.

FIG. 5 is a block diagram of a conventional example.

6 is a time chart of the pattern generation circuit of FIG.

[Explanation of symbols]

 1 ・ 11 ・ 21 ・ 31 Main register 2 ・ 5 ・ 17 ・ 27 ・ 37 Selection circuit 4 Output register 6 ・ 61 Sequence circuit 7 Timing generator 8 Frequency divider circuit 9 Sequence control circuit 10 Control memory 12 ・ 22 ・ 32 ALU circuit 13 ・ 23 ・ 33 Auxiliary register 14 ・ 24 ・ 34 Timing generator 15 ・ 25 ・ 35 Sequence controller 16 ・ 26 ・ 36 Control memory

Claims (4)

[Claims] 1. A timing generation circuit (7) for generating a system clock, and a divided clock (8) for dividing the system clock into a plurality of frequencies.
Frequency divider circuit (8) that outputs A) and sequence control circuit that controls a predetermined program command
(9) and a control memory (10) for storing the program instruction
, A main register (1) for storing pattern data, an auxiliary register (13, 23, 33) for storing operation data for the output of the main register (1), output data of the main register (1) and the By selecting one of the plurality of ALU circuits (12, 22, 32) for calculating the output data of the auxiliary registers (13, 23, 33) and one of the outputs of the plurality of ALU circuits (12, 22, 32) A pattern generation circuit comprising: a first selection circuit (2) for outputting to the main register (1). 2. A retiming circuit (41, 42, 43) for retiming the outputs of the plurality of ALU circuits (12, 22, 32) in synchronization with the divided clock (8A), and the retiming circuit. A second selection circuit (5) for rearranging the outputs from (41, 42, 43) serially; and an output register (4) for retiming the output of the second selection circuit (5) with the system clock. 2. The pattern generation circuit according to claim 1, further comprising a sequential circuit (6) for controlling the second selection circuit (5). 3. A timing generation circuit (7) for generating a system clock, and a divided clock (8) for dividing the system clock into a plurality of frequencies.
Frequency divider circuit (8) that outputs A) and sequence control circuit that controls a predetermined program command
(9) and a control memory (10) for storing the program instruction
And multiple main registers (11, 21, 3 for storing pattern data).
1), an auxiliary register (13,23,33) for storing operation data for the outputs of the plurality of main registers (11,21,31), and output data of the plurality of main registers (11,21,31) And one of the plurality of ALU circuits (12,22,32) for computing the output data of the auxiliary registers (13,23,33) and the output of the plurality of main registers (11,21,31) And the plurality of ALUs
A pattern generation circuit comprising: a first selection circuit (17, 27, 37) for outputting to a circuit (12, 22, 32). 4. A second selection circuit (5) for serially rearranging outputs from the plurality of main registers (11, 22, 31).
And an output register (4) for retiming the output of the second selection circuit (5) with the system clock, and a sequential circuit (6) for controlling the second selection circuit (5). The pattern generation circuit according to claim 3, wherein