JPS6288434A - Analog/digital converting circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably the number of components, to decrease a chip area attended therewith and to improve the operating speed by providing a switching circuit, a latch circuit and an adder circuit so as to increase the bit number of resolution. CONSTITUTION:Switching circuits 11, 12 each having a resistor and a switch and giving a prescribed offset voltage to each comparison voltage act like outputting two kinds of comparison voltages. The two kinds of comparison voltages are coded by a comparator 13 and an encoder 14 to output two kinds of digital signals. A latch circuit 15 holds one digital signal and the one digital signal and the other digital signal are added by an adder circuit 16. Thus, the number of bits of the resolution is increased.

Description

Detailed Description of the Invention (Industrial Use ￥f) The present invention uses a number of comparators corresponding to the number of bits to determine the comparison voltage that matches the analog input voltage at once, and converts the analog input voltage into a digital signal. This invention relates to an A/D conversion circuit using a parallel comparison method.

(Prior art) Conventionally, there was a technology in this field described in Hisashi Yoneyama, [Illustrated Introduction to A/B Converter] (September 25, 1980), Ohmsha P, 117-120. .

The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional M-bit parallel comparison type A/D conversion circuit.

This A/D conversion circuit includes a comparison voltage generation circuit 1, a comparator section 2, and an encoder 3.

The comparison voltage generation circuit l is a circuit that divides the reference voltage VR into a plurality of voltages and outputs each divided voltage as comparison voltages v1 to V2M-1, and has 2M units connected in series between the reference voltage VR and the ground. The voltage dividing resistor R is made up of equal voltage dividing resistors R.

The comparator section 2 has a plurality of comparison voltages Vt to V2M-1.
and an analog input voltage VT to output an output signal corresponding to the comparison, and is composed of (2M-1) comparators Al-A2M-1. Each comparator A
l-A2M-1 is composed of a capacitor, a differential amplifier, and the like.

The encoder 3 is a circuit that encodes the output signal of the comparator section 2 and outputs 20 to 2M digital signals vO.
It consists of an OR gate (hereinafter referred to as an OR gate) and an OR gate (hereinafter referred to as an OR gate).

In the configuration of -1- below, the reference voltage VR is divided by 2M equal voltage dividing resistors R, and these voltages are the comparison voltage V.
l~V2M-1 to Lte each converter Al-A2M
-1 is input. Each comparator ^I-A2M-1 compares the comparison voltage Vl-V2M-1 with the analog input voltage VI, outputs an output signal corresponding to the comparison voltage, and outputs an output signal to the encoder 3. These output signals -) are VT > Vl ~
V2M-1 throat logic “1”, Vl<Vl ~
V2N-1[7] Logic “0” roars. The encoder 3 outputs 20 to 2M digital signals vO based on the output signals of the respective comparators A1 to A2M-1. In this way, the analog input voltage vI is converted into an M-bit digital signal vO.

This type of A/D conversion circuit uses (2M-1) comparators Al-A2"-1 to determine the comparison voltages v1 to V2"-1 that match the analog input voltage VI at once, so high-speed processing is possible. It has the advantage that it can be done.

(Problems to be Solved by the Invention) However, the I-structure acid circuit has the following problems.

Resolution (Least 51gn1ficant Bit
) When increasing the LSB from M bits to N (>M) bits, the number of voltage dividing resistors R and comparators A1 to A2M-1 increases by (2N-2M). For example, resolution LSB
from 3 bits to 4 bits -(-Geroto, voltage dividing resistor R
And the number of comparators A1 to ^2M-1 increases by a factor of two. Therefore, as the chip area increases, the overall value of the voltage-dividing resistor H increases, and the comparators A1 to A
There was a problem in that it took time to charge and discharge the capacitors constituting the 2M-1, which hindered high-speed operation. In particular, when the number of elements in the voltage dividing resistor R and comparators A1 to A2M-1 increases, the relative accuracy (variation) between each element increases.
If it is not limited to a higher precision, the operating speed will decrease, so in order to obtain a certain high-speed operation, it is necessary to manufacture highly accurate elements with no manufacturing variations.

The present invention solves the problem that the conventional technology had, in that increasing the number of bits of resolution by 1 significantly increases the number of circuit components, which increases the chip area and reduces the operating speed. The present invention provides an A/I) conversion circuit that solves the problem.

(Means for Solving the Problem) In order to solve the above problem, the present invention provides a comparison voltage generation circuit that outputs a plurality of comparison voltages, and a plurality of comparison voltage generation circuits that compare the plurality of comparison voltages and an analog input voltage. An A/D conversion circuit comprising a comparator and an encoder that encodes the output signal of the comparator and outputs a digital signal, wherein the switching circuit includes a resistor and a switch and makes each of the comparison voltages have a predetermined offset voltage. , a latch circuit that temporarily holds the digital signal, and an adder circuit that adds the output of the latch circuit and the digital signal.

(Function) According to the present invention, since the A/D conversion circuit is configured as shown below, the switching circuit works to output two types of comparison voltages, and these two types of comparison voltages are connected to the comparator and The encoder encodes the signal and outputs two types of digital signals. The latch circuit holds one digital signal, and the one digital signal and the other digital signal are added by the 7G circuit. This increases the number of bits of resolution. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of an A/D conversion circuit showing a first embodiment of the present invention.

This A/D conversion circuit is an N-bit parallel proportional A/D converter.
II; Comparison pressure generation circuit 10. Switching circuits 11, 12, comparator fjR]3. The encoder 14 includes a latch circuit 15 and an adder circuit 16.

The comparison voltage generation circuit IO is a circuit that divides the reference voltage VR into a plurality of voltages and outputs each divided voltage as a comparison Ill voltage, and includes 2N equal voltage dividing resistors R1- connected in series.
It is composed of R2H. Comparison voltages v1 to V2N appear at the voltage dividing points of the voltage dividing resistors R1 to R2N, respectively.

The switching circuits 11 and 12 are circuits that provide a predetermined offset voltage (for example, resolution 1.SB/2) to the comparison voltages v1 to V2N. The 91 converter circuit 11 on the - side has a resistor of 172 of the voltage dividing resistor R1 (11!; anti-r
and a changeover switch SWI, the Jlt and resistor r are connected to the voltage dividing point between the voltage dividing resistors R1 and R2, and an S, 11 changeover switch SWI is connected between the resistors r and R1 and the ground. It is connected. The changeover switch SWI grounds the voltage dividing resistor R1 when switched to one terminal 5WIa side, and grounds the resistor r when switched to the other terminal 5Wlb side. A resistor r having a resistance value of
, A selector switch SW2 is connected between R2H and the reference voltage VR.
is connected. When the changeover switch SW2 is switched to the one terminal 5W2a side, it applies a quasi-voltage VR to the voltage dividing resistor R2N, and when it is switched to the other terminal 5W2b side, it applies the reference voltage VR to the resistor r.

The comparator section 13 has a plurality of comparison voltages Vl to V2N.
and an analog voltage VT and outputs an output signal corresponding to the comparison, and is composed of 2N comparators A1 to A2N consisting of capacitors, differential amplifiers, and the like.

The encoder 14 is connected to the output side of the comparator section 13, and encodes the output signal of the comparator section 13 to generate 211 digital signals 320 to 32N-1.
(2N-2) (7) EXOR gates E1 to E2N-1 and N OR gates) Gl to GN
It is made up of. Furthermore, the encoder 14 directly outputs an overrange (OVR) output S obtained from the comparator A2'' of the least significant bit.
B/2) It is too big, Compa L/-)) A
This is a signal generated when 2N becomes logic 11111.

A latch circuit 15 and an adder circuit 16 are connected to the output side of the encoder 14. The latch circuit 15 receives digital signals S20 to S which are the outputs of the OR gates 01 to GN.
This circuit temporarily holds the signal 2 and 1 and supplies the signal to the adder circuit 16, and is composed of a D-type flip-flop and the like. The adder circuit 1B is a circuit that adds the output of the latch circuit 15 and the output of the OR gate Gl''GN to output (20 to 2N) digital signals VO. gate), etc.

The operation of the A/mouth conversion circuit configured as described above will be explained with reference to the A/mouth conversion characteristic diagrams shown in FIGS. 3 and 4.

Here, in order to simplify the explanation, the A/port conversion circuit is
The analog input voltage v1 range (full scale range FSR) is 8V, and the resolution LSB is tV.
Assume that In a 4-bit A/D conversion circuit.

Voltage dividing resistor RI NH4N = R1-R8 reference voltage Vl
-V2N =V1-VB Comparator Al-A2N =A1~A8EXOREI
~F2N-1=E1~E7OR gate GI NGN=
G1-G3 digital signal S20-52N-1=52
0 to S22 output signal vO number -20 to 23.

First, move one selector switch SW1 to the terminal 5Wla side,
Switch the other changeover switch SW2 to the terminal 5W2a side, and set the analog input voltage Vll to VI5 (
However, 1. , O≦VII <Vl2 <Vl3 <Vl4
<Vl5<8). Then, comparison voltages v1 to v8 appear at each voltage division point of the comparison voltage generation circuit 10, and are applied to each of the comparators A1 to A8 together with analog input voltages VII to VI5. Compare the two-man power of each parator A1-88, Vll ~ VI5 > Vl ~ V8
(7) Apply a logic “1” signal to VTI to VI5.
<When Vl~v8, a logic "O°" signal is outputted to the EXOR gates E1~E7 of the encoder 14, respectively.
j-er.

Each of the EXOR gates EI to F7 outputs a signal of logic "1" when the two manpowers are different, and a signal of logic "0" when the two manpowers are the same, and applies them to the OR gates G1 to G3. OR game) Gl~G3 is one or more of multiple inputs -1
If − is logic “l”, the output will be logic “l”, so
Digital signals 520-922 having 3-bit output codes are output from the OR gates GI-G3. Then, the latch circuit 15 receives the digital signals S20 to S22.
Latch. Such 3-bit quantization A/D conversion characteristics are shown by solid curve A in FIG.

Next, connect each changeover switch SWI, SW2 to terminal 5W1b,
Switch to the 5W2b side. Then, at each voltage division point of the comparison voltage generation circuit 10, LSB/
A comparison voltage offset by 0.2 (=0.5V) appears, and is applied to each comparator Al-A3 together with the analog input voltages VTI to VI5. The comparison voltage applied to the comparator 1 router A I-A8 is compared with the analog input voltage Vll-VI5 in the same manner as described above, and then converted into a 3-bit output code by the encoder 14, and the digital signal s20 to S22 are applied to the adder circuit 16. Such A/D conversion characteristics are shown by the broken line curve B in FIG.

The adder circuit 1G adds the output of the latch circuit 15 and the digital signals S20 to S22 after offset, and generates 4 bits as shown in the following 3-bit/4-bit conversion truth table.
A digital signal vo of bits 20 to 23 is output.

3-bit/4-bit conversion truth table mL, encoder output code (1); Output code of solid curve A in Figure 3 Encoder output code (2); Output code S of broken line curve B in Figure 3 ; Overrange OVR output vO code ; Output code of adder circuit I6.
As shown in the figure.

This embodiment has the following advantages.

(1) For example, when achieving a resolution of 8 LSB bits using the method of this embodiment with the number of bits N = 7, the conventional circuit requires 28-1 = 255 comparators and 2B = 258 voltage dividing resistors. In contrast, the circuit of this embodiment has 128 comparators and 131 voltage dividing resistors.

The plane area occupied by one comparator is 29120 p, t
a? (80gX384 IL), the planar area occupied by one voltage dividing resistor is 12800p, m2 (80μXl80
pL), if an 8-bit circuit is configured using a conventional circuit, the plane area occupied by all comparators and voltage dividing resistors is approximately 10.
It becomes 7mm2. On the other hand, the planar area occupied by all the comparators and voltage dividing resistors in the circuit of this example is approximately 5
．． It becomes 4mm2. In addition, newly added latch circuit 15
The planar area occupied by the adder circuit 16 is 144000I.
Since it is L intestine 2 (120 pL x 1200 pL), the area ratio is approximately 1/2, and when it is integrated into an integrated circuit (IC), the chip area can be significantly reduced.

Also, A/+1 with a resolution of 8 bits on the board (board) -L
When assembling a conversion circuit, if the circuit of this embodiment is used, the number of components can be reduced by half compared to the conventional circuit, as described above.

(2) In the conventional circuit, when the resolution LSB becomes -
Since the voltage dividing resistors are connected in series, the overall other resistance value becomes large, and it takes time to charge and discharge the capacitor forming the comparator. On the other hand, in this embodiment, the resistor value for voltage division can be set to 172, which is the conventional value.
The time for charging and discharging the capacitor is reduced to 1/2 of the conventional time.
This is useful when operating at high speed.

FIG. 5 is a configuration diagram of an A/D conversion circuit showing a second embodiment of the present invention.

This A/El conversion circuit differs from the fJSl embodiment in that the circuit configuration of the switching circuits 21 and 22 is different.

That is, in the -power v1 conversion circuit 21, a voltage dividing resistor R1 and switch SW21 connected in series, and a resistor R and switch 5W22 connected in series are connected in parallel between the voltage dividing resistor R2 and the ground. ing.

In the other switching circuit 22, the terminal 5W of the switching switch 2
2b and the voltage dividing resistor R2N connected in parallel.
resistors R and R are connected. Further, a voltage dividing resistor R2N is connected to the terminal 5W2a of the changeover switch 2,
The configuration is such that the reference voltage VR is applied to the resistor R1R or the voltage dividing resistor 1'12N via the changeover switch SW2. Here, the valley resistance R in the switching switches 21 and 22 has the same resistance value as the voltage dividing resistors R1 to R2N.

In the above configuration, first, the switch SW21 is turned on, and the changeover switch SW2 is switched to the terminal 5W2a side to convert the analog input voltage Vl into a digital signal.

This operation is similar to that of the first embodiment. Next, to offset the reference voltage by LSB/2, switch 5
11122 is also turned on, and the selector switch SW is turned on.
2 to the terminal S2b side. Then, the resistance value of one switching circuit 21 becomes R/2, which is equal to the resistance r of the first embodiment, and the resistance value of the other switching circuit 22 also becomes R/2, which is equal to the resistance r of the first embodiment. It becomes equal to the resistance r in the example. Therefore, the same digital conversion operation as in the first embodiment is performed.

This A/D conversion conversion circuit point is connected to each resistor R1 to R2N, R in the comparison voltage generation circuit lO and the switching circuit 21.22.
are all set to the same resistance value. Therefore, when integrating these into an integrated circuit, they can all be patterned into the same shape using polysilicon resistors, etc., and this reduces the relative accuracy, or variation, between each resistor and improves the operating speed.
- can be measured.

In the A/D conversion circuit of 1, when the analog input voltage v is an alternating current signal t) like a blind spot signal and is to be converted into a digital signal t), as shown in Fig. 5, a predetermined A sample-and-hold circuit 30 that extracts and holds the analog input terminal Vl for a certain amount of time may be connected to the input terminals of the comparators A1 to A2N.

If the analog input voltage Vl is an AC signal as described above,
If the AC signal changes during A/D conversion, accurate 47-channel conversion becomes impossible. Therefore, if the sample-and-hold circuit 30 is provided, this sample-and-hold circuit 3
0 maintains the analog input voltage Vl at a constant value until the operation of the analog circuit (comparison voltage generation circuit IO and comparator section 13) in the A/D conversion conversion circuit is completed, so that accurate A/D conversion is possible. can be done.

In addition, in the embodiment described in -, the comparison voltage generation circuit 10,
The switching circuits 11, 12, 21, 22, encoder 14, etc. can be modified to a circuit configuration other than that shown in the drawings.

(Effects of the Invention) As described in detail below, according to the present invention, since the switching circuit, latch circuit, and adder circuit are provided, the number of circuit components can be significantly reduced compared to the conventional one. Accordingly, the chip area can be reduced and the operating speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram of an A/D conversion conversion circuit showing a first embodiment of the present invention, FIG. 2 is a diagram of a conventional A/D conversion conversion circuit, and FIG. 3 is a diagram of a conventional A/D conversion conversion circuit.
3 and 4 are characteristic diagrams of the 3-bit and 4-bit quantity conversion A/D conversion characteristics shown in FIG. . 10... Comparison voltage generation circuit, 11, 12, 21
．． 22...Switching IT [8, 13...Comparator section, 14...Encoder, 15...
...Latch circuit, 1B...Adder circuit,
R1~R2N...Resistance for voltage division, r, R...
...Resistance, enemy 1. SW2, 5W21, 5W22...
···switch. -King Toro Rlow ■ 1') 3 choices 1] -f

Claims (1)

[Scope of Claims] A comparison voltage generation circuit that divides a plurality of reference voltages and outputs each divided voltage as a comparison voltage, and compares the plurality of comparison voltages with an analog input voltage and outputs an output signal corresponding to the comparison voltage. an A/D conversion circuit comprising a plurality of comparators that encode the output signal and output a digital signal; An A/D conversion circuit comprising: a latch circuit that temporarily holds the digital signal; and an adder circuit that adds the output of the latch circuit and the digital signal.