JPS628860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data reproducing circuit that detects the absence of a framing code within a predetermined period, erases the contents of the memory, invalidates incorrect data, and extracts only correct data to an external circuit. The purpose of the present invention is to provide a data reproducing circuit that can perform the following functions.

The present applicant has developed an electrode function in which the main information signal and the reference signal for tracking control to accurately trace the regenerating needle to the information signal pit are recorded as changes in the geometrical shape, without first forming a needle guide groove. The main information signal and tracking control reference signal are read and reproduced as changes in capacitance by relative sliding scanning between a disk-shaped information recording medium (hereinafter referred to as disk) and a reproduction needle having an electrode function. proposed a playback device.
In addition, in the above-mentioned disk, the video signal is recorded as the main information signal in 4 fields per revolution on the spiral main track, and the main information signal is recorded at, for example, 17H from the fall of the vertical synchronization signal during the vertical retrace period. The chapter data representing the number, and the time data representing the recording position (address) of the main information signal at the 18th H are converted to biphasic code (hereinafter referred to as FM code) and recorded as data of 1 and 0, respectively. .

FIG. 1 shows an example of a block system diagram of a data reproducing circuit of an information recording medium reproducing apparatus previously proposed by the present applicant. The FM code recorded on the disc is converted into an electrical signal by the playback needle, and then demodulated as a video signal. The PCM signal (FM code) multiplexed in a specific horizontal scanning period within the vertical retrace period of the demodulated video signal enters the input terminal 1 via a suitable data extraction circuit (not shown).
This PCM signal is supplied to a clock regeneration circuit 2 to regenerate a clock signal synchronized with the data cycle, and is also supplied to a data regeneration circuit 3 to regenerate a data signal together with the regenerated clock signal, which is then supplied to the memory 5. The data signal is taken out as an NRZ signal by the clock timing of the clock signal taken out from the clock regeneration circuit 2 via the clock switching circuit 4 into the memory 5 (having the data block length of the PCM signal) constituted by, for example, a shift register. The terminal 10 outputs an output from the terminal 10 to an external circuit as required.

The PCM signal input to input terminal 1 includes a framing code of, for example, 1H period to delimit data blocks, and if clock regeneration circuit 2 and data regeneration circuit 3 operate correctly, When the signal is correctly reproduced from the disk, the framing code detection circuit 6 detects the framing code, and the detection signal is taken out from the framing code detection circuit 6 to set the flip-flop 7. Therefore, the flip-flop 7 records the presence or absence of a framing code. By setting the flip-flop 7, a ready signal for informing an external circuit (not shown) that a data signal has entered the memory 5 is taken out from the output terminal 8, while the clock switching circuit 4 is connected to the clock regeneration circuit 2.
Switch from the side to the terminal 9 side. The external circuit inputs a read clock from terminal 9 in response to a ready signal, and reads data stored in memory 5 from terminal 10.
The external circuit reads the data in the memory 5 until the next vertical synchronization signal. Flip-flop 7 is terminal 1
It is reset by the vertical synchronization signal from 1.

By the way, for example, if the playback signal disappears due to a dropout or the like during disk playback, the memory 5 remains unfilled with data, and when new data comes in in this state, the remaining data is sequentially filled. It is shifted out of the shift register. As a result, although the data in one horizontal scanning period including this signal loss is incorrect data and should be invalidated, the framing code is detected based on the data remaining in the memory 5 and the newly arrived data. There is a problem in that circuit 6 is activated, the framing code is extracted, and a ready signal is output to the external circuit, resulting in incorrect data being output to the external circuit. Correction means using wear was necessary.

The present invention solves the above problems, and one embodiment thereof will be described below with reference to FIG. 2.

FIG. 2 shows a block system diagram when an embodiment of the data reproducing circuit according to the present invention is applied to an information recording medium reproducing apparatus. In the figure, the same parts as in FIG. 1 are given the same numbers. In the same figure, normal PCM
When a signal is received and clock reproduction and data reproduction are operating normally, the flip-flop 7 is set by the detection signal from the framing code detection circuit 6, and a ready signal is taken out from the terminal 8.
The external circuit is informed that the data in this one horizontal scanning period is readable normal data, and the same operation as in FIG. 1 is performed. At this time, since the output of flip-flop 7 is at L level, nothing is output from AND circuit 12. In other words, the contents of the memory 5 are normally read out to the external circuit by the read clock from the terminal 9.

Here, if a dropout occurs during one horizontal scanning period, the framing code detection circuit 6 does not operate because the memory 5 is not filled with a predetermined amount of data. As a result, the flip-flop 7 is not set and its output becomes H level, and when the next horizontal synchronizing signal is input to the input terminal 13, the output of the AND circuit 12 becomes H level, and a reset signal is supplied to the memory 5. The contents are set to zero. That is, all data in one horizontal scanning period in which dropout occurred is canceled.

Therefore, even if new data comes in one horizontal scanning period after a dropout or the like has occurred in one horizontal scanning period, the contents of the memory 5 during the one horizontal scanning period in which the dropout occurred will be reset to zero and then replayed. Since this starts, there is no risk that a framing code will be detected by the remaining data and the next new data as in the circuit shown in the first diagram.

Although the above embodiment was explained using a disk as an example, the same configuration can be applied to a PCM signal multiplexed in the vertical blanking period of a video signal such as a VTR, and In the case of a PCM signal that does not have a synchronization signal, even if a periodic signal corresponding one-to-one in time to the period of the framing code is created by means such as detecting no signal from the framing code or other appropriate signal, the above-mentioned You can get the same effect as .

As mentioned above, the data reproducing circuit according to the present invention has the following features:
If the content stored in the framing code storage circuit is without a framing code due to the periodic signal having a one-to-one time relationship with the period of the framing code, a function is provided to once reset the contents of the memory to zero at the time the periodic signal is generated. Therefore, if the playback signal disappears due to a dropout, etc., the memory remains unfilled with data, and even if new data comes in in this state, the contents of the memory during the predetermined period when the dropout occurred will be erased. Therefore, the framing code will not be detected between the data left in memory and the next new data.
It has features such as being able to inform external parties of only correct data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of an information recording medium reproducing apparatus previously proposed by the applicant, and FIG. 2 is a block diagram of an embodiment of the circuit of the present invention. 1...Digital time series signal input terminal, 2...Clock regeneration circuit, 3...Data regeneration circuit, 5...
Memory, 6...Framing code detection circuit, 7
...Flip-flop, 8...Ready signal output terminal, 10...Data output terminal, 12...AND circuit, 13...Horizontal synchronization signal input terminal.

Claims (1)

[Claims] 1. A memory that demodulates a digital time-series signal having a framing code and stores the information, a framing code detection circuit that detects the framing code from the signal, and an output of the framing code detection circuit. a framing code storage circuit that stores the presence or absence of the framing code and notifies the outside that the digital time series signal is stored in the memory based on the presence of the framing code; and means for reading the contents of the memory. In a data reproducing circuit with a periodic signal that temporally corresponds one-to-one with the period of the framing code, if the content stored in the framing code storage circuit is without a framing code, the periodic signal is generated at the time when the periodic signal is generated. A data reproducing circuit characterized by being provided with means for once zeroing the contents of a memory. 2. Claim 1, wherein the digital time series signal is a signal that is multiplexed into the horizontal scanning period within the vertical retrace period of the television signal, and the periodic signal is a horizontal synchronization signal. The data reproducing circuit described in section.