JPS63104151A - Microprocessor containing tracing function - Google Patents

Abstract

PURPOSE:To obtain a unified tracing function by using a prefetch unit, a memory control unit, a bus control unit, a micro ROM, a microsequencer and an executing unit. CONSTITUTION:A prefetch unit 1 prefetches an instruction to be carried out from a main memory and decoded. Then the unit 1 produces an effective operand address and sends it to a memory control unit 2. The unit 2 contains a TLB for execution of conversion at a high speed. A bus control unit 3 puts a real address sent from the unit 2 on an external bus and gives accesses to the memory and an I/O. A microsequencer 4 produces the address of a microprogram based on the instruction decoding information received from the unit 1 and also accepts various interruptions to reflect them onto the program address. A micro ROM stores the microprogram. Thus it is possible to improve the software evaluation efficiency and to carry out a tracing job without using any additional device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor having an address trap function, and particularly to tracing of the address trap.

(Prior Art) Conventionally, this type of microprocessor does not seem to be equipped with an address trap trace function. In such a microprocessor, as an alternative means, an external device such as an in-circuit emulator is used, and a trace function of the device is used.

(Problems to be Solved by the Invention) In the conventional microprocessor described above, an external device must be used to realize the trace function.

Therefore, since it is necessary to attach a device adapter or the like to the socket of the microprocessor, there is a drawback that the device must be brought to the user's site for troubleshooting analysis and the like.

An object of the present invention is to detect a match between an address at the time of memory access and a preset address, notify the microprogram of the match as an interrupt for generation of an address comparison trap, and control trace on/off. Another object of the present invention is to provide a microprocessor with a trace function that eliminates the above-mentioned drawbacks and is configured so that a trace machine can be integrated therein.

(Means for Solving the Problems) A microprocessor with a trace function according to the present invention includes a prefetch unit, a memory management unit, a hash control unit, a micro ROM, a micro sequencer, and an execution unit. It is something.

The prefetch unit is for preemptively decoding an instruction to be executed and generating an effective operand address.

The memory management unit receives the effective operand address sent from the prefetch unit and also converts the virtual address into a real address.

The bus control unit compares the real address sent from the memory management unit with the effective operand address sent from the prefetch unit, and if the two match, puts the real address on the external bus and executes access to the device. It is for the purpose of

Micro ROM is for storing micro programs.

The microsequencer generates microprogram addresses based on instruction decode information from the prefetch unit, accepts interrupts due to address comparison traps if necessary for tracing, and reflects them in the microprogram addresses. .

The execution unit is for actually executing instructions.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microprocessor with a trace function according to the present invention.

In FIG. 1, 2 is a memory management unit, 3 is a bus control unit, 4 is a micro sequencer, 5 is a micro ROM, and 6 is an execution unit.

In FIG. 1, a prefetch unit 1 prefetches an instruction to be executed from a main memory (not shown), decodes it, generates an effective operand address, and sends it to a memory management unit 2. The memory management unit 2 is a unit that converts virtual addresses sent from each unit into real addresses. The memory management unit 2 has a TLB inside to realize high-speed conversion. The bus control unit 3 puts the real address sent from the memory management unit 2 onto the external bus, and accesses the memory and the device 10. The microsequencer 4 generates the address of the υ microprogram based on the instruction decode information from the prefetch unit 1.

It also accepts various interrupts and reflects them on the microprogram address. The micro ROM 5 stores micro programs. The execution unit 6 is a unit that actually executes instructions, and its internal configuration is made up of a VJ, P, ALU, a barrel shifter, and the like.

The bus control unit 3 has a function of comparing an address during memory access such as instruction 7 etch or operand read/write with a preset address and detecting a match.

This function must generate an address comparison trap when it detects a match between addresses.

Therefore, a notification is sent to the microsequencer 4 via the interrupt signal line 7 as an address comparison trap generation interrupt.

When an address comparison trap interrupt occurs, the microprogram generates an address comparison trap, sets a trap number, and enters the trap processing routine.

Since the microprocessor with trace function shown in FIG. 1 has the trace function of the address comparison trap, it performs the processing shown in FIG. 2. As shown in FIG. 2, first, the trace on/off control flip-flop is checked to determine whether or not tracing is to be executed. If trace is on, necessary information such as the program counter and matching address is written to a predetermined memory area.

Thereafter, the address comparison trap number is set in the same way as for trace-off, and the trap processing is performed (7). In trap processing, trap information is stored in a predetermined memory area, and a trap processing software program called a trap handler is run.

(Effects of the Invention) As explained above, the present invention detects a match between an address during memory access and a preset address, notifies the microprogram of the match as an address comparison trap interrupt, and turns on tracing. By controlling /off, it is possible to trace the occurrence of address comparison traps on-chip without any additional equipment, and by improving the address comparison logic, it is also possible to compare addresses at multiple locations simultaneously. effective.

Another advantage is that addresses can be completely masked and comparisons can be made with addresses that have a range.

By tracing such address comparison traps, the efficiency of software evaluation can be improved and tracing can be performed without the presence of additional equipment.

This has the effect that the cause of the failure can be easily analyzed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprocessor with a trace function according to the present invention. FIG. 2 is a 70-chart showing the execution of the address comparison trap interrupt processing microprogram. 1... Pre-7 etching unit 2... φ memory management unit 3... Bus control unit 4... Working micro sequencer 5... Micro ROM 6... Execution unit 7... Signal line

Claims (1)

[Claims] a prefetch unit that preemptively decodes an instruction to be executed and generates an effective operand address; and a memory management unit that receives the effective operand address sent from the prefetch unit and converts a virtual address into a real address. Then, the real address sent from the memory management unit is compared with the effective operand address sent from the prefetch unit, and if the two match, the real address is placed on the external bus and access to the device is performed. A bus control unit for executing the microprogram, a microROM for storing the microprogram, and an address for the microprogram is generated based on instruction decode information from the prefetch unit, and interrupts due to address comparison traps are also necessary for tracing. 1. A microprocessor with a trace function, comprising: a micro sequencer for accepting instructions, if any, and reflecting them in the address of the microprogram; and an execution unit for actually executing instructions.