JPS6310536Y2 - - Google Patents
Info
- Publication number
- JPS6310536Y2 JPS6310536Y2 JP9274983U JP9274983U JPS6310536Y2 JP S6310536 Y2 JPS6310536 Y2 JP S6310536Y2 JP 9274983 U JP9274983 U JP 9274983U JP 9274983 U JP9274983 U JP 9274983U JP S6310536 Y2 JPS6310536 Y2 JP S6310536Y2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- flip
- output
- input
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000000819 phase cycle Methods 0.000 claims description 7
- 229910001219 R-phase Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000018199 S phase Effects 0.000 description 2
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【考案の詳細な説明】
本考案は相順検出回路に関する。相順の検出器
として従来より回転式の検相器があるが、これは
ハード的な回路中に相順を確認するような回路と
して組込むようなことは不可能であり、又、さら
に小型化できない。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase sequence detection circuit. Conventionally, there is a rotary phase detector as a phase order detector, but it is impossible to incorporate this into a hardware circuit as a circuit to check the phase order, and further miniaturization is required. Can not.
本考案は三相電気装置の現地調整等に手軽に使
用できるような小型で安価でしかも、相順の確認
回路として他の回路中にも組込める相順検出回路
の提供を目的とする。 The object of the present invention is to provide a phase sequence detection circuit that is small and inexpensive and can be easily used for on-site adjustment of three-phase electrical equipment, and can also be incorporated into other circuits as a phase sequence confirmation circuit.
第1図は本考案による相順検出器の回路構成図
である。図中、F1〜F3はRSフリツプフロツプ、
F4はJKフリツプフロツプ、ORはオアー素子、
ANDはアンド素子、(但し、後記のバツフアが
PNP型トランジスタで構成されるときはナンド
素子とする。)、Bはトランジスタ等で入力信号を
増巾して出力するバツフア、Lは発光ダイオー
ド、D1〜D6はダイオード、I1〜I3はインバータ、
C1〜C4はコンデンサ、R1〜R13は抵抗である。こ
のような回路構成に於て、抵抗R1〜R3の入力側
にそれぞれ三相電源RSTを接続する。そして、
R相、S相、T相が図示のように正しい相順で入
力されると、発光ダイオードLに60Hzの電源が流
れて点灯し、逆にR相、S相、T相の相順が逆相
で入力されると、発光ダイオードLには電流が流
れないため点灯しない。この結果よりRSTが正
相順か逆相順かを判別できるようにしたものであ
る。以下第2図を参照して第1図の動作を説明す
る。まず、第1図の回路に三相電源が接続される
と、ダイオードD4〜D6で整流され、直流電圧
Vccが得られ(C4はリツプルをとるためのもの)
発光ダイオードLのアノード側に印加される。
又、一方、各相の電圧はダイオードD1〜D3でそ
れぞれ半波整流され、RSフリツプフロツプF1〜
F3のセツト入力端子S、及びインバータI1〜I3を
介してリセツト入力端子Rに入力される。(ここ
で、C1〜C3,R10〜R12はノイズとりのために挿
入されているものである)したがつて、図示のよ
うに正相順で三相電源に接続された場合は、フリ
ツプフロツプF1〜F3の出力端子Qからの出力は
それぞれ第2図イ〜ハに示す波形となる。又、
JKフリツプフロツプF4はフリツプフロツプF1の
出力が負論理でリセツト入力端子に入力されたと
き、すなわち、低電位“L”が印加されている期
間リセツトされるため第2図ニに示すような期間
でリセツトされる。このような条件のものとで、
JKフリツプフロツプF4のクロツク入力端子Cに
フリツプフロツプF2,F3の出力がオアー素子OR
を介して入力される。したがつてF2の出力の立
上り時点でF4は反転して“H”出力を出すが他
方、F3の出力の立上り時点ではJKフリツプフロ
ツプF4のR端子に低電位“L”が印加されてい
るため、C端子にF3の出力が入力されてもフリ
ツプフロツプF4は反転しないため、フリツプフ
ロツプF4の出力は“L”のままとなる。したが
つて、F4の出力は第2図ホの波形となる。 FIG. 1 is a circuit diagram of a phase sequence detector according to the present invention. In the figure, F 1 to F 3 are RS flip-flops,
F 4 is a JK flip-flop, OR is an OR element,
AND is an AND element (however, the buffer described later is
When configured with a PNP transistor, it is a NAND element. ), B is a buffer that amplifies the input signal using a transistor etc. and outputs it, L is a light emitting diode, D 1 to D 6 are diodes, I 1 to I 3 are inverters,
C1 to C4 are capacitors, and R1 to R13 are resistors. In such a circuit configuration, a three-phase power supply RST is connected to the input sides of the resistors R1 to R3 , respectively. and,
When the R phase, S phase, and T phase are input in the correct phase order as shown in the diagram, 60Hz power flows to the light emitting diode L and it lights up, and conversely, the phase order of the R phase, S phase, and T phase is reversed. When input in phase, no current flows through the light emitting diode L, so it does not light up. Based on this result, it is possible to determine whether RST is in positive phase order or reverse phase order. The operation shown in FIG. 1 will be explained below with reference to FIG. First, when a three-phase power supply is connected to the circuit shown in Figure 1, it is rectified by diodes D4 to D6 , and the DC voltage
Vcc is obtained (C 4 is for taking ripple)
It is applied to the anode side of the light emitting diode L.
On the other hand, the voltage of each phase is half-wave rectified by diodes D 1 to D 3 and RS flip-flops F 1 to F 3 .
It is input to the reset input terminal R via the set input terminal S of F3 and the inverters I1 to I3 . (Here, C 1 to C 3 and R 10 to R 12 are inserted to remove noise.) Therefore, when connected to a three-phase power supply in positive phase order as shown in the figure, , the outputs from the output terminals Q of flip-flops F1 to F3 have the waveforms shown in FIG. 2A to C, respectively. or,
The JK flip-flop F4 is reset when the output of the flip-flop F1 is input to the reset input terminal in negative logic, that is, during the period when the low potential "L" is applied, so the period shown in FIG. It will be reset. With such conditions,
The outputs of flip-flops F 2 and F 3 are connected to the clock input terminal C of JK flip-flop F 4 as an OR element.
Input via . Therefore, at the time when the output of F2 rises, F4 is inverted and outputs "H", but on the other hand, at the time when the output of F3 rises, a low potential "L" is applied to the R terminal of the JK flip-flop F4 . Therefore, even if the output of F3 is input to the C terminal, flip-flop F4 is not inverted, so the output of flip-flop F4 remains "L". Therefore, the output of F 4 has the waveform shown in FIG. 2 (E).
この結果、アンド素子ANDの出力は正相入力
の場合は第2図ヘのような電流バツフアBを介し
て、発光ダイオードLに流せしめることとなる。
一方、逆相の状態で入力された場合はF4の出力
“H”とF3の出力“H”とが重なる時点がないた
め、第2図トのように発光ダイオードLには全く
電流が流れないこととなる。したがつて、正相相
入力の場合は60Hzの電流で発光ダイオードLが点
灯するが、逆相入力の場合は全く点灯しないこと
から相順の検出が可能となる。 As a result, in the case of a positive phase input, the output of the AND element AND is made to flow to the light emitting diode L via the current buffer B as shown in FIG.
On the other hand, if the input is in a reverse phase state, there is no point at which the output "H" of F4 and the output "H" of F3 overlap, so there is no current in the light emitting diode L as shown in Figure 2. It will not flow. Therefore, in the case of a positive phase input, the light emitting diode L lights up with a current of 60 Hz, but in the case of a negative phase input, it does not light up at all, making it possible to detect the phase order.
以上の実施例では発光ダイオードを点灯させて
検出する場合を示したが、他の回路に本回路を組
込む場合は、他の回路で60Hz波形の有無を相順検
出波形として使用するようにすればよい。したが
つて、本考案により、小型且つ安価で、しかも、
他回路中にも組み込める相順検出回路が得られる
こととなる。 The above example shows the case where detection is performed by lighting up a light emitting diode, but if this circuit is incorporated into another circuit, the presence or absence of the 60Hz waveform can be used as a phase sequential detection waveform in the other circuit. good. Therefore, the present invention is small, inexpensive, and
A phase sequence detection circuit that can be incorporated into other circuits is obtained.
第1図は本考案による相順検出回路の実施例の
回路構成図、第2図は第1図の動作説明用の波形
図である。
FIG. 1 is a circuit configuration diagram of an embodiment of a phase sequence detection circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of FIG. 1.
Claims (1)
素子D1,D2,D3;それぞれ前記該当相の整流素
子の出力をセツト入力端子Sに入力するとともに
同じ整流素子の出力をインバータIを介してリセ
ツト入力端子Rに入力する、各相毎に設けたR・
SフリツプフロツプF1,F2,F3;前記三個の
R・Sフリツプフロツプ中の第2相目と第3相目
用のフリツプフロツプF2,F3のセツト出力を入
力するオアー素子OR;前記オアー素子ORの出
力をクロツク入力端子Cに入力するとともに前記
R相用のRSフリツプフロツプF1の出力を負論理
でリセツト入力端子Rに入力するJKフリツプフ
ロツプF4;前記JKフリツプフロツプF4の出力及
び前記S相用のRSフリツプフロツプF2の出力を
入力するアンド素子AND又はナンド素子;で構
成した相順検出回路。 Rectifying elements D 1 , D 2 , D 3 to which the three-phase AC voltage is input for each phase; the output of the rectifying element of the corresponding phase is input to the set input terminal S, and the output of the same rectifying element is input to the inverter I. The R.
S flip-flops F 1 , F 2 , F 3 ; OR elements OR that input the set outputs of flip-flops F 2 and F 3 for the second and third phases among the three R.S flip-flops; A JK flip-flop F4 inputs the output of the element OR to the clock input terminal C, and also inputs the output of the R-phase RS flip-flop F1 to the reset input terminal R in negative logic; the output of the JK flip-flop F4 and the S A phase sequence detection circuit consisting of an AND element or a NAND element that inputs the output of the phase RS flip-flop F2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9274983U JPS60566U (en) | 1983-06-15 | 1983-06-15 | Phase sequence detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9274983U JPS60566U (en) | 1983-06-15 | 1983-06-15 | Phase sequence detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60566U JPS60566U (en) | 1985-01-05 |
| JPS6310536Y2 true JPS6310536Y2 (en) | 1988-03-29 |
Family
ID=30223115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9274983U Granted JPS60566U (en) | 1983-06-15 | 1983-06-15 | Phase sequence detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60566U (en) |
-
1983
- 1983-06-15 JP JP9274983U patent/JPS60566U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60566U (en) | 1985-01-05 |
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