JPS631053A - Semiconductor nonvolatile ram - Google Patents

Abstract

PURPOSE:To prevent the flowing of excess junction working currents on erasing, and to simplify and miniaturize the constitution of a semiconductor nonvolatile RAM coupled with an EEPROM by forming an erasing region in the EEPROM in regions except a drain. CONSTITUTION:An erasing electrode 7 forming an EEPROM storing the memory contents of a semiconductor nonvolatile RAM and recalling by erasing is shaped outside a drain region 3, not on the drain region 3. Consequently, even when high voltage is applied for erasing to the electrode 7 on recall, erasing currents do not flow through the region 3 as junction leakage currents, and memory contents stored in a floating gate 6 are transferred to the nonvolatile RAM and erased. Accordingly, erasing currents can be reduced, and a high-voltage generating circuit can be manufactured in a small-sized type one having small current capacitance with the reduction of erasing currents, thus simplifying and miniaturizing the semiconductor nonvolatile RAM to be coupled with the EEPROM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile RAM used in electronic equipment such as computers.

[Summary of the invention]

The present invention provides an electrically rewritable RO, which is a component of a semiconductor nonvolatile memory, in a semiconductor nonvolatile RAM.
By improving the structure of M, a semiconductor nonvolatile RAM with a large amount of information can be provided.

[Conventional technology]

A conventional semiconductor nonvolatile RAM is shown in FIG. 2 (al).

A transistor TI is connected to the node A of the Scutinok RAM.
T2 and the third are connected.

(References; I[iEE Journal of 5
did 5tate circuits vol 5
c-18m5 PP525 ~ 531) [Point J while the invention is trying to solve] Conventional semiconductor non-volatile RA as shown in Fig. 2 [al.
In M, when erasing the EEPROM (electrically rewritable read-only memory) second information for storing static RAM M, a transistor T,
approximately 18V to the drain region of transistor T2 via
high voltage is applied.

A cross-sectional view of this EEF ROM is shown in Figure 2).

For this reason, when attempting to integrate a conventional semiconductor nonvolatile RAM with a high bit density, leakage occurs between the drain region to which a high voltage is applied and the substrate. ii) The amount of current has increased, and the area of the high voltage generation circuit formed within the integrated circuit has become extremely large. That is, it has been difficult to manufacture inexpensive semiconductor nonvolatile memories because the integrated circuits have become larger.

The present invention has been made to overcome the above-mentioned drawbacks, and an object of the present invention is to form an inexpensive semiconductor nonvolatile memory with a small integrated circuit area.

[Means for solving problems]

The problem mentioned above is that the erase region that transfers charges into and out of the floating gate, which is one of the charge storage mechanisms of EEPROM, is
This occurred because it was formed on the drain like bl. In order to solve this problem, the present invention adopts a configuration in which the erase region is not provided on the drain. Specifically, a first channel forming region electrically coupled to a storage node of a volatile memory, a second channel forming region electrically coupled to the first channel forming region, and a second channel forming region electrically coupled to the first channel forming region; Second
a channel forming region, a third channel forming region electrically coupled to each other, a first gate electrode for controlling a first channel formed in the first channel forming region, and a second channel forming region. a charge storage mechanism provided on the region; a second gate electrode that controls the charge of the charge storage mechanism or a second channel formed in the second channel formation region; and the third channel formation region. and a reproducing region electrically coupled to the third channel forming region. "Electrically coupled with the channel forming region" refers to being electrically conductive directly or through a third region when a channel is formed,
The charge storage mechanism means a layer that non-volatilely holds electrons, a genuine plate, etc., such as a floating gate or a multilayer insulating film structure, or a layer that can maintain a polarized state, such as a strong XAM body layer. The second gate electrode is a large insulated gate when controlling the second channel, but is it connected to the charge storage mechanism during erase and store operations? There may be cases where there is an inflow or outflow of J style. In some cases, the charge storage mechanism performs erasing and storage by flowing charges into and out of the second channel forming region using the voltage of the second gate electrode. Furthermore, the first. The second gate may be connected to the second channel forming region by forming a short barrier, a heterojunction, a pn junction, or via an insulating film; When the charge storage device F1 is a floating gate and has an overlapping portion with the floating gate through an insulating film so thin that current flows when a high voltage is applied between the floating gates, the charge storage mechanism It can be used for erasing operations by transferring charges in and out. A plurality of second gate electrodes may also be provided.

Note that the storage node J of the F volatile memory is ta+ in FIG.
It means a node in a circuit that stores information electrically, such as node A, or a physical information storage area of a memory or static memory, which will be described later.

[Effect]

E[By forming the erase region of an EPROM in a region other than the drain, the erase region does not form a semiconductor junction with other regions, so that an excessive junction leakage current due to high voltage application does not flow and the EEPROM can be erased. Information can be deleted. Alternatively, since no high voltage is applied to the semiconductor junction during erasing, leakage current is small. Therefore, it is possible to provide a low-cost semiconductor non-volatile memory because the high voltage generation circuit (1 current capacity) is small.Furthermore, the uni-cell configuration is smaller in area or has a smaller number of elements than the conventional N V RAM.
can be realized.

〔Example〕

A first embodiment of the semiconductor nonvolatile RAM of the present invention will be described with reference to FIGS. 1 and 3 to 7.

FIG. 1 shows a first embodiment of a semiconductor nonvolatile RAM of the present invention. An EEFROM surrounded by a broken line is connected to node C of the static RAM. FIG. 3 shows a cross-sectional view of the EEFROM applicable to the present invention, surrounded by this broken line. This EEPROM uses a P-type semiconductor substrate l.
Alternatively, a source region 2 and a drain region 3 (operating as a reproducing region) of the N' region are formed at a distance from each other on the surface of a P-type channel forming region separated in the substrate, and a A gate electrode 4 is formed on the channel formation region y5 (first, second and third channel formation regions).
(operates as the first gate electrode) and floating gate electrode 6
(charge storage mechanism) and erase electrode (abbreviated as EC) 7 (third
(acting as gate electrodes) are formed in series. In addition, on the floating gate electrode CFG) 6, a control Jl
A control gate)'m1 (abbreviated as Cc)5 (operates as a second gate electrode) is formed through the il gate oxide film 9. The erase electrode 7 and the floating gate electrode are the erase insulating film 2.
It has opposing parts via I.

First, the store operation of the semiconductor nonvolatile memory of the present invention will be explained. The store operation refers to transferring information from static RAM to EEF ROM. First, a high voltage of about 20 V is applied to the erase electrode 7 to extract electrons in the floating gate electrode 6 through the erase four-color frame film. At this time, channel 2? The potential of the first gate electrode 4 must be set so that a does not flow. Next, about 20V is applied to the control gate electrode 5.
Apply a high voltage of At this time, the potential of the first gate electrode 4 is as follows: in FIG. 1, when the potential of the node C is at a high level, the first channel is OFF;
Set the level so that the channel turns on. Also,
The potential of the erase electrode 7 is such that the third channel below it is OFF.
Set to the potential.

When the level of node C shown in FIG. 1 is high, gate t
Since the first channel under i4 is OFF, even if the potential of the floating gate electrode 6 is high via the control gate voltage pi15, the electric charge of the floating gate electrode 5 is reduced because no descendant electric field is applied to the tunnel insulating film 8. The amount does not change much. That is,
Maintain the post-tnn state. Conversely, when the voltage level of node C shown in figure yj1 is low, the potential of the second channel under floating gate electrode 6 is equal to the potential of node C because the channel under gate electrode 1 is in the ON state. It will be the same.

Therefore, the system? '[ll Through the gate electrode 5, the floating gate T! When a high voltage is applied to the pole 6, a high electric field is applied to the tunnel insulator 8, and electrons are injected into the floating gate electrode 6 from the second channel forming region on the surface of the substrate 1.

As described above, when the voltage level of the node C in FIG. 1 is high, the potential of the )7 floating gate electrode 16 is positively charged. Conversely, when the voltage level of node C is low, t7
The potential of the release gate electrode 6 becomes negative 11F. Immediately, the RAM is huge! The left one is in the EIEPROM (there are many). In this way, a store operation is performed in which the ↑ blue clothes of RΔ~1 are transferred to the EIEPROM.

Next, the transfer of information from the ROM to the RAM, that is, the recall operation will be explained.

First, the TL source voltage of flAM is lowered to approximately zero level. Next, the level of the node RC in FIG. 1 is set to a high level, and the first channel under the gate TL pole 4 is turned on.
I'll do what I do. Further, a voltage is applied to the erase electrode 7 so that the third channel region under the erase electrode 7 is also turned on. When the floating gate Ti and the pole 6 are positively charged, the negative region under the floating gate electrode 6 is also turned on, so that the level of the node C in FIG. 1 becomes equal to the level of the node 'D.

In other words, it becomes a high level. Conversely, when the floating gate is negatively charged, the second channel region under the floating gate 7:L pole 6 is OFF, so the level of node C in FIG. It is not equal to the level of node D. In this case, design the RAM so that the level of node C is low.As mentioned above, if the potential of r7 floating gate electrode 6 is positively charged, When the level of node C becomes a high potential and is negatively charged, the level of node C becomes a low potential.

In this way, the information in the ROM is transferred to the RAM, and a recall operation is performed.

FIG. 4 shows an example of using a MONO3 type element as an EEPROM, and shows a case where it is formed in a well region 20 formed on the surface of the substrate 1.

21 is a first channel forming region, 22 is a second channel forming region, and 23 is a third channel forming region. The other numbers correspond to FIG. 3, but in this case, the charge storage mechanism 6 is a silicon nitride film.

And carriers formed at the interface with the SiC2 film!
8 is a Si film thin enough to allow electrons to tunnel through it, and 9 is a SiC2 film that is thicker than 8. The first gate electrode 4 and the third gate electrode 7 control the channels of the first channel forming region and the third channel forming region via the gate insulating film 10, and are insulated from the second gate electrode 5. There is. The second gate electrode 5 controls the channel of the second channel forming region via the insulating film 8.9° charge storage mechanism 6.

FIG. 5 shows a second embodiment in which the EEFROM shown in FIG. 4 is coupled to a storage node C of a static memory to constitute a nonvolatile RAM. In the figure, G + , G z
, G 3 are the first . Second. Third gate? ilt
At the pole, S is the source region and 'D is the reproduction region.

In the store operation of this embodiment, the EEFROM is an n-chable and is a MONOS type memory, so that
The explanation will be made assuming that the erase start voltage is ±5. First, in order to clear the memory contents of EEPROM, G2
Apply -7v to By this operation, electrons in the charge storage mechanism are emitted into the channel forming region 21 through the tunnel insulation film 8. Next, a voltage lower than the dark value voltage of the third channel is applied to G, and a potential equal to the average value of the potential of node C in the "0" state and "1" state plus approximately Ga) II value voltage is applied to G1. put. If node C is in “D° state, then E
The source potential of the EPROM will be at a value close to OV, the first channel will conduct and pump carriers (in this case electrons) into the second channel, and the charge storage mechanism on the second channel will be filled with charge (in this case negative electrons). charge) is accumulated. - way,
If the node C is in the 11'' state, the source potential of the EEFROM is at such a high potential that the first channel cannot conduct, so there is no accumulation of N charges in the charge accumulation mechanism. So, the static memory information is E
A store operation is performed to move to EFROM.

Regarding the recall operation, it can be performed in the same manner as in the first embodiment.

Next, as a third embodiment of the present invention, FIG. 6 shows a case in which an NVRAM with a small unit cell area is constructed using a floating gate type EEFROM and a Guinaminok memory as shown in FIG. 3. In Figure 6, QA is the address 'Mt
Indicates a transistor for R, P indicates a capacitor for information storage, and R indicates EEPl? used in this application. Represents OM. The store operation is almost the same as in the second embodiment. In this case, E.E.
It is assumed that charges flow into and out of the charge storage mechanism of the PROM through the tunnel insulating film 8. The recall operation is performed as follows. First, set the digit line to low level,
The word line is set to high level, and the address selection transistor Q
, writes a low level into the information storage capacitor P, and then sets the word line to a low level. (If necessary, the digit line is also set to high level.) Next, the reproduction area is set to high level, and Gl+GLG3 is set to high level. At this time, if negative charges are accumulated in the charge accumulation mechanism, EE
R of the PROM is not conductive and the state of the information storage capacitor remains at a low level. If no negative charge is stored in the charge storage mechanism, R of the EEFROM becomes conductive and the state of the information storage capacitor changes to high level. A recall operation is performed in this manner. FIG. 7 shows a sectional view of an embodiment in which the circuit diagram of FIG. 6 is realized as an integrated circuit. R
is an EEPRO having a structure as shown in FIGS. 3 and 4.
1, the source region 2 is omitted, and the first channel forming region and the storage node C are provided continuously. 30 is a semiconductor region formed on the surface of a semiconductor substrate or separately formed on a semiconductor substrate, or a semiconductor region formed on an insulating substrate, and 31, 32, and 33 are the first . The second and third channel forming regions 34 are continuous with the first channel forming regions. In the semiconductor region of the information storage capacitor P of the dynamic memory, 35 is a channel formation region of the address selection insulated gate FETQA of the dynamic memory. 130 is a daisy/ ) region forming a rectifying junction of the semiconductor region 30, and is also a source or drain region of QA. 111
110 is the insulating film of the information storage capacitor P, and 110 is the information storage capacitor P. a conductive electrode facing the semiconductor region 34 of the storage capacitor P;
121 is number Il! ! The gate insulating film of the insulated gate FETQA for selection, 120, is the gate electrode of the insulated gate FETQA for address selection.

In the configuration shown in FIG. 7, if the amount of charge stored in the phase storage capacitor of the dynamic memory (stored in region 34) is small, sufficient charge may not be injected into the charge storage mechanism of the EEFROM. In this case ITh 8m
The film 111 is made thin enough to allow a Fakler-Nordheim tunneling current to flow, and the film 111 is made thin enough to allow a Fakler-Nordheim tunneling current to flow.
A memory element according to the principle shown in the figure is a semiconductor zl region 3.
4. When composed of the insulating film 111 and the opposing region 110, EE
Since the carriers supplied to the charge storage mechanism of the PROMR are constantly supplied from P which has become capable of static memory operation, sufficient writing is possible.

Also in this case, the first channel forming region of the EEPROM is electrically connected to the storage node C of the MIS type static memory.

〔Effect of the invention〕

As described above, according to the semi-destructive RAM of the present invention, only the maximum power supply voltage is applied to the semiconductor region provided in the substrate during storage, so that the storage operation can be performed with a small amount of current. Become. Semiconductor non-volatile RAM is RAM
information is transferred to ROM at once. That is, all bits of ROM
Store together. Therefore, according to the semiconductor nonvolatile RAM according to the present invention, even if the number of bits increases, the current of the high voltage application electrode required at the time of storage is extremely small, so that the storage operation can be easily performed. Even if the number of bits increases, the area of the high voltage generation circuit within the integrated circuit is small and storage operations can be performed. Furthermore, according to the present invention, the number of elements in a unit cell and the cell area can be reduced. Therefore, it is possible to provide an inexpensive high-bit semiconductor nonvolatile RAM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor non-volatile RAM according to an embodiment of Section 1 of the present invention, FIG. 2 (al is a circuit diagram of a conventional semiconductor non-volatile RAM, and FIG. Cross-sectional view of EEPROM used in non-volatile RAM, Part 3
The figure shows E used in the semiconductor nonvolatile RAM of the present invention.
FIG. 4 is a cross-sectional view of an EEFROM that can be used in the present invention, and FIG. 5 is a cross-sectional view of EEFROM in FIG.
FIG. 2 is a circuit diagram of a second embodiment of a nonvolatile RAM using an EPROM. FIGS. 6 and 7 are a circuit diagram and a sectional view of semiconductor nonvolatile RAMs according to the third and fourth embodiments of the present invention, respectively. 1...P-semiconductor substrate 2...\°Source region 3...No Drain region 4...Gate electrode 5...Control gate electrode 6...Floating seedling gate electrode 7...Erasing electrode 8...Tunnel insulation■ri 21...Erase insulating film or more

Claims (1)

[Claims] A first channel, forming region electrically coupled to a storage node of a volatile memory; a second channel, forming region electrically coupled to the first channel forming region; a third channel forming region electrically coupled to the second channel forming region; a first gate electrode controlling a first channel formed in the first channel forming region; and a first gate electrode controlling the first channel formed in the first channel forming region; a charge storage mechanism provided on the formation region; a second gate electrode for controlling the charge of the charge storage mechanism or a second channel formed in the second channel formation region; and a third channel formation region. It is composed of at least a third gate electrode that controls a third channel formed in the region, and a reproduction region that is electrically coupled to the third channel forming region, and the charge accumulated in the charge storage mechanism is A semiconductor nonvolatile RAM characterized in that air flows into or out of at least one of the first gate electrode, the second gate electrode, the third gate electrode, and the second channel forming region.