JPS63120423U - - Google Patents

Info

Publication number
JPS63120423U
JPS63120423U JP1037587U JP1037587U JPS63120423U JP S63120423 U JPS63120423 U JP S63120423U JP 1037587 U JP1037587 U JP 1037587U JP 1037587 U JP1037587 U JP 1037587U JP S63120423 U JPS63120423 U JP S63120423U
Authority
JP
Japan
Prior art keywords
offset
converter
reference level
detecting
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1037587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1037587U priority Critical patent/JPS63120423U/ja
Publication of JPS63120423U publication Critical patent/JPS63120423U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案にかかるA/Dコンバータのオ
フセツトキヤンセル回路を示すブロツク図、第2
図はオフセツト説明図である。 10…A/Dコンバータ、12…切替スイツチ
、14…ラツチ回路、15…オフセツト調整回路
、16…D/Aコンバータ、18…減算回路、2
0…コントローラ。
FIG. 1 is a block diagram showing an offset cancel circuit of an A/D converter according to the present invention, and FIG.
The figure is an offset explanatory diagram. 10... A/D converter, 12... Selector switch, 14... Latch circuit, 15... Offset adjustment circuit, 16... D/A converter, 18... Subtraction circuit, 2
0...Controller.

Claims (1)

【実用新案登録請求の範囲】 基準レベルを一時的にA/Dコンバータに入力
させる基準レベル入力手段と、 前記基準レベルが入力されているときのA/D
コンバータの出力からオフセツトを検出するオフ
セツト検出手段と、 検出されたオフセツトに基づきアナログ信号の
A/D変換時に、当該オフセツトに応じたレベル
だけアナログ信号より減算してA/D変換コンバ
ータの入力信号とするオフセツト調整手段とを備
えたことを特徴とするオフセツトキヤンセル回路
。
[Claims for Utility Model Registration] Reference level input means for temporarily inputting a reference level into an A/D converter, and an A/D converter when the reference level is input.
an offset detection means for detecting an offset from the output of the converter; and an offset detection means for detecting an offset from the output of the converter; 1. An offset cancel circuit comprising an offset adjustment means for adjusting the offset.
JP1037587U 1987-01-27 1987-01-27 Pending JPS63120423U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1037587U JPS63120423U (en) 1987-01-27 1987-01-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1037587U JPS63120423U (en) 1987-01-27 1987-01-27

Publications (1)

Publication Number Publication Date
JPS63120423U true JPS63120423U (en) 1988-08-04

Family

ID=30796605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1037587U Pending JPS63120423U (en) 1987-01-27 1987-01-27

Country Status (1)

Country Link
JP (1) JPS63120423U (en)

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