JPS63122169A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63122169A JPS63122169A JP61268216A JP26821686A JPS63122169A JP S63122169 A JPS63122169 A JP S63122169A JP 61268216 A JP61268216 A JP 61268216A JP 26821686 A JP26821686 A JP 26821686A JP S63122169 A JPS63122169 A JP S63122169A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pad
- bonding
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装直に関し、特にポンディングパッドの
電極構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to improvements in the electrode structure of bonding pads.
ＧａＡａを用いた電界効果トランジスタ（以後、ＧａＡ
ａ Ｆ Ｅ ’ｆと称す）のゲート電極及び外部ＩＪ−
ド取シ出し用のポンディングパッド部は一般にＭ族又は
ｈ４合金展で形成されており、又ポンディングパッド部
と半導体容器のリード端子を接続するためのボンディン
グワイヤーは一般に２０〜３０μｍφの金脈が用いられ
ている。Field effect transistor using GaAa (hereinafter referred to as GaA
a F E 'f) gate electrode and external IJ-
The bonding pad section for lead extraction is generally made of M group or H4 alloy, and the bonding wire for connecting the bonding pad section and the lead terminal of the semiconductor container is generally made of a gold vein of 20 to 30 μmφ. It is used.
第３図社この様な従来のボンディングパット部の断面図
を示したものであり、１は半導体基板、２はＡｌｊＬ３
は金線、４は絶縁膜である。Figure 3 shows a cross-sectional view of such a conventional bonding pad part, where 1 is a semiconductor substrate, 2 is an AljL3
4 is a gold wire, and 4 is an insulating film.
しかしながら、この様な従来のパッド構造には以下に述
べる二つの大きな欠点がある。即ち、第１の欠点はｆｊ
ＫＫｕ帯以上の超高周波用のＧａＡｓＦＥＴではゲート
パッドのもつ寄生容量による利得低下を防ぐ為、ゲート
パッドの大きさは一般に３０μｍ０以下に設計されるが
、パッド面積の縮小に伴って半導体基板とＡｌ膜の接着
強度が低下し、ボンディング時にパッド部がしばしば剥
れるという欠点があシ、歩留低下の大きな要因となって
いる。第２の欠点はｈ６換２に金線３を直接ボンデイン
クすると、長時間動作でＡ！とＡｕが反応してＡｕＡＪ
！、いわゆるパープルブレークが生じ、コンタクト抵抗
が増大して断線に至る。という欠点がアシ、信頼性低下
の一因となっている。However, such conventional pad structures have two major drawbacks as described below. That is, the first drawback is fj
In GaAsFETs for ultra-high frequencies above the KKu band, the gate pad size is generally designed to be 30 μm or less in order to prevent gain reduction due to parasitic capacitance of the gate pad. The bonding strength of the bonding layer decreases, and the pad portion often peels off during bonding, which is a major factor in lowering yield. The second drawback is that if you bonde the gold wire 3 directly to the h6 exchange 2, it will work for a long time. and Au react to form AuAJ
! , a so-called purple break occurs, and contact resistance increases, leading to disconnection. This shortcoming is one of the causes of decreased reliability.
本発明は、この様な従来の欠点を除去し、ボンディング
時に電極剥れの発生しない、又パープルブレークの発生
しない電極構造を有する半導体装置を提供するものであ
る。The present invention eliminates these conventional drawbacks and provides a semiconductor device having an electrode structure that does not cause electrode peeling or purple break during bonding.
上述した従来の電極構造は半導体基板上にＡ！膜を形成
し、この上（ＨＡｕから成るボンディングワイヤーで接
続する方法をとっている。これに対し本発明は、ｈｔＭ
形成前に予じめ半導体基板表面を異方性エツチングによ
シ表面に凹凸を形成して粗面化し、実効的な表面積を増
大させて半導体基板とＡ！膜との接着強度を高め、さら
ＫＡＪＢとＡｕ膜の間に高融点金属を介在させて反応防
止を計るという独創的内容を有する。The conventional electrode structure described above has A! A method is used in which a film is formed and a bonding wire made of HAu is used to connect the film.On the other hand, the present invention
Before formation, the surface of the semiconductor substrate is roughened by anisotropic etching to form irregularities on the surface to increase the effective surface area. It has an original content that increases the adhesive strength with the film and also prevents reactions by interposing a high melting point metal between the KAJB and the Au film.
本発明の半導体装置は、異方性エツチングによシ粗面化
された半導体基板上にＡ！又はＡ１合金電極が設けられ
、さらにその上に高融点金属又は高融点金属窒化膜を介
して金膜を被覆したパッドが設けられ、該パッドに金線
が接続された構造を有している。The semiconductor device of the present invention has A! Alternatively, it has a structure in which an A1 alloy electrode is provided, a pad covered with a gold film via a high melting point metal or a high melting point metal nitride film is provided thereon, and a gold wire is connected to the pad.
以下、実施例として、ＧａＡａ ｆ半導体基板として用
いた場合を例にと）図面を用いて詳細に説明する。Hereinafter, as an example, a case where a GaAa f semiconductor substrate is used will be described in detail with reference to the drawings.
第１図は本発明にかかる一笑施例の電極パッド部の断面
図で、半導体基板１の粗面化された表面１′上に例えば
約６０００１ＯＡ！換２を形成し、その上に例えば約２
０００１の窒化チタン（ＴｉＮ）膜５を被着し、更にそ
の上に例えば約５ｏｏｏＸのＡｕ膜６ｔ−形成してＡｕ
膜６にＡｕ線３をボンディングしている。FIG. 1 is a cross-sectional view of an electrode pad portion of an embodiment according to the present invention, in which approximately 60,001 OA! 2 and on top of which, for example, about 2
A titanium nitride (TiN) film 5 of 0001 is deposited, and an Au film 6t of about 500
The Au wire 3 is bonded to the film 6.
半導体基板１の粗面化は苛性ソーダ水溶液と次亜塩素酸
ナトリウム水溶液の混合液を用いて表面をエツチングす
ることにより得られる。この混合液を用いると、結晶万
位依存性が強く、特に（１１１） ｒＭのエツチング速
度が（１００） ［ｉｉに比べ遅いことから、エツチン
グは一様に進行せず表面に凹凸が形成され粗面化される
。Ａｌｇ２は蒸着法で、ＴｉＮＪｌ１５およびＡｕ膜６
はスパッタ法で被着される。仁の様な電極構造にすれば
、パッド面積が３０μＴｒＬ０程度と小さくなっても１
板表面に凹凸が形成される為、実効的な表面積が増大し
ボンディング強度が増大する。実際にボンディング強度
試験を行った結果、粗面化を行っていない時の′［執剥
れの発生率は約２０％であったのに対し、粗面化を適用
することにより皆無となった。The surface of the semiconductor substrate 1 can be roughened by etching the surface using a mixed solution of a caustic soda aqueous solution and a sodium hypochlorite aqueous solution. When this mixture is used, there is a strong crystal orientation dependence, and in particular, the etching rate of (111) rM is slower than that of (100) [ii], so the etching does not proceed uniformly and the surface becomes uneven and rough. Faced. Alg2 was deposited by vapor deposition, TiNJl15 and Au film6
is applied by sputtering. If the electrode structure is made like this, even if the pad area is as small as 30μTrL0,
Since irregularities are formed on the plate surface, the effective surface area increases and the bonding strength increases. As a result of an actual bonding strength test, the incidence of peeling was approximately 20% when the surface was not roughened, but it was completely eliminated by applying the surface roughening. .
爽にこの様な電極構造にすれば、ＴｉＮ 展５が反応防
止層としてＡｌ膜２とＡｕ膜６０間に介在するのでパー
プルブレークが発止しない。実際、２９５℃の高温保管
を１２時間実施した後も、特に外観上及びコンタクト抵
抗に伺ら変化はみられなかった。If such an electrode structure is used, the TiN spreader 5 is interposed between the Al film 2 and the Au film 60 as a reaction prevention layer, so that purple break does not occur. In fact, even after 12 hours of high-temperature storage at 295° C., no changes were observed in terms of appearance or contact resistance.
また、第２図は本発明にかかる他の実施例の断面図で、
Ａｌｇ２の上にＴｉＮ ａ５、続いて例えば２ｏｏｏＸ
ｔｖｐｔｙｔｉｒｔ被着し、ＪｌｉｌミニソノＪｌｌえ
ば約１μｒｎ ＯＡ ｕめっき層８を形成した電極パッ
ドの例である。ｐｔ膜７は金めつき層８の給電用及びバ
リヤメタルとして介在させた膜で、この様な構造におい
ても同様にパープルブレークが防止できることは勿論で
ある。Moreover, FIG. 2 is a sectional view of another embodiment according to the present invention,
TiN a5 on top of Alg2 followed by e.g. 2oooX
This is an example of an electrode pad on which a plating layer 8 of approximately 1 μrn OA u is deposited. The PT film 7 is a film interposed as a power supply and barrier metal for the gold plating layer 8, and it goes without saying that purple break can be similarly prevented in such a structure.
上記の実施例は反応防止層ｔ−ＴｉＮ農で形成したもの
であるが、ＴｉＮ腺の代りにＷ、Ｎｏ、Ｔａ等の高融点
金属を用いても同様の効果が得られる。In the above embodiment, the reaction prevention layer is formed of t-TiN, but the same effect can be obtained by using a high melting point metal such as W, No, Ta, etc. in place of the TiN layer.
以上の説明から明らかなように、本発明によればワイヤ
ボンディング時の電極剥れ及びパープルブレークを防止
でき、半導体装置の歩留及び信頼性の著しい向上が可能
となった。As is clear from the above description, according to the present invention, electrode peeling and purple break during wire bonding can be prevented, and the yield and reliability of semiconductor devices can be significantly improved.
第１図およぶ第２図は本発明にかかる電極ベッド部の断
面図、第３図は従来の電極パッド部の断面図である。
図において、ｌ・・・・・・半導体基板、１・・・・・
・粗面部、２ ・・・・−Ａｌ Ｍ、 ３ ・−・−Ａ
ｕ ＰＪ、４・・・・・・絶縁膜、５・・・・・・Ｔｉ
Ｎ展、６・・・・・・Ａｕ膜、７・・・・・・ｐｔ農、
８・・・・・・Ａｕめつさ層を示す。
等 ｌ 図1 and 2 are cross-sectional views of an electrode bed portion according to the present invention, and FIG. 3 is a cross-sectional view of a conventional electrode pad portion. In the figure, l...semiconductor substrate, 1...
・Rough surface part, 2...-Al M, 3...--A
u PJ, 4...Insulating film, 5...Ti
N exhibition, 6...Au film, 7...PT agriculture,
8... Indicates an Au metal layer. etc. l diagram
Claims (1)
ｌ又はＡｌ合金電極が設けられ、さらにその上に高融点
金属又は高融点金属窒化膜を介して金膜を被覆したパッ
ドが設けられ、該パッドに金線が接続された構造を有す
ることを特徴とする半導体装置。A on a semiconductor substrate roughened by anisotropic etching.
It is characterized by having a structure in which a l or Al alloy electrode is provided, a pad covered with a gold film via a refractory metal or a refractory metal nitride film is provided thereon, and a gold wire is connected to the pad. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268216A JPS63122169A (en) | 1986-11-10 | 1986-11-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268216A JPS63122169A (en) | 1986-11-10 | 1986-11-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63122169A true JPS63122169A (en) | 1988-05-26 |
Family
ID=17455526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61268216A Pending JPS63122169A (en) | 1986-11-10 | 1986-11-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63122169A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010157683A (en) * | 2008-12-03 | 2010-07-15 | Renesas Technology Corp | Semiconductor integrated circuit device |
| WO2021115436A1 (en) * | 2019-12-13 | 2021-06-17 | 成都今是科技有限公司 | Microelectrode of gene sequencing chip, manufacturing method therefor, and gene sequencing chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50131764A (en) * | 1974-04-05 | 1975-10-18 | ||
| JPS55163884A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor light emitting element |
-
1986
- 1986-11-10 JP JP61268216A patent/JPS63122169A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50131764A (en) * | 1974-04-05 | 1975-10-18 | ||
| JPS55163884A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor light emitting element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010157683A (en) * | 2008-12-03 | 2010-07-15 | Renesas Technology Corp | Semiconductor integrated circuit device |
| WO2021115436A1 (en) * | 2019-12-13 | 2021-06-17 | 成都今是科技有限公司 | Microelectrode of gene sequencing chip, manufacturing method therefor, and gene sequencing chip |
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