JPS63123221A - Min/max circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Summary of the Invention The MIN circuit consists of a comparator and a compensator, and the MAX circuit similarly consists of a comparator and a compensator. If such a MIN circuit and a MAX circuit are connected in cascade, the compensator for both circuits can be omitted (see FIGS. 1, 2, and 9 to 11).

BACKGROUND OF THE INVENTION The present invention relates to a MIN/MAX circuit in which a MIN circuit and a MAX circuit are connected in cascade. This M.I.N.
The /MAX circuit is preferably used in fuzzy inference engines.

The great human brain has the concept of stored programs,
He created a digital computer by combining pool algebra and stable binary hardware. This continuous operation has made it possible to develop deep logic and perform deep processing of data. Digital computers are highly reliable due to their stable operation, and digital computer systems are becoming increasingly large. As long as the program does not contain information on a human mental level, a digital computer can be programmed with anything, and in this respect it can even be called a general-purpose machine.

With the realization of digital computer systems, human life9 and society are undergoing major changes.

Another great human brain considered what and how humans think and how they communicate with each other, and created the extremely important concept of ``fuzziness.'' L,
A. Zadch proposed the concept of fuzzy sets in 1.
The year is 985. Since then, many papers have been published on fuzzy theory, but there are still few reports on its application, and the reality is that it has only been done with the help of binary digital computers.

In fuzzy research, 9 human knowledge is based on accumulated experience that should be summed up with linguistic information, like the know-how of experts. That is emphasized. This linguistic information is generally characterized by ambiguity, ambiguity, uncertainty,
It is characterized by incompleteness or inaccuracy and by a membership function. Membership size is 0
．． It is expressed by a numerical value in the range between 0 and 1.0,
It varies within this range.

When linguistic information is handled by a digital computer, the membership magnitude (value) is represented by a pinary φ code. The values represented by this binary code are stored, transferred, and operated on in binary electronic circuitry over and over again according to the stored program. Therefore, there is a problem in that it takes a long time to process fuzzy information by digital systems. Additionally, binary-encoded values require an incredibly large number of storage and operation devices. Although digital computers are general-purpose machines as mentioned above, they are not necessarily optimal for processing fuzzy information in real time.

There is a need to explore other types of machines that can process fuzzy information efficiently and quickly.

SUMMARY OF THE INVENTION The present invention provides an M(N/MAX circuit) which is particularly suitable for use in a fuzzy inference engine that is essential in a hardware system suitable for processing fuzzy information, that is, a new system called a "fuzzy φ computer." There is a particular thing.

In the MI N/MAX circuit according to the present invention, a plurality of three-terminal control elements each having an input input to a control terminal and having a carrier injection terminal connected in common and serving as an output terminal are connected to the three terminals to which the smallest input is applied. A comparator for MIN calculation in which the control elements are connected so as to be in a conductive state, and a plurality of three-terminal control elements whose control terminals each receive an input and whose carrier injection terminals are commonly coupled and serve as output terminals. is connected so that the 3-terminal control element to which the largest input is applied is in a conductive state.
It is characterized in that comparators for calculation are connected in cascade.

The MI N/MAX circuit has a MIN circuit connected to the front stage and a MAX circuit connected to the rear stage, and a MAX circuit connected to the front stage M
It includes both circuits with an IN circuit connected to the latter stage.

A typical three-terminal control element is a transistor, which includes not only bipolar transistors but also MOS FETs and the like. The control terminal corresponds to the base or gate, and the carrier injection terminal corresponds to the emitter or source.

The MIN circuit is composed of a comparator for the above-mentioned MIN operation and a compensator for compensating for a voltage shift in the comparator (for example, a voltage drop vEB between emitter and base). Similarly, the MAX circuit is composed of a comparator for the above-mentioned MAX operation and a convencator for compensating for the voltage shift in this comparator. Since the MIN circuit compensator and the MAX circuit compensator compensate for voltage shifts in opposite directions, these compensators can be omitted when the MIN circuit and MAX circuit are connected in cascade. In this way, the MIN/MAX circuit according to the present invention does not require any elements to constitute a compensator, resulting in a simple two-circuit configuration, and the number of elements such as transistors used can be saved.

As detailed in the description of the Examples.

A MIN operation or a MAX operation is often used in the calculations of a fuzzy inference engine, which is an element of a fuzzy combination. When constructing a hardware system that executes these operations, a MIN circuit and a MAX circuit are required, and these circuits may be connected in cascade. At that time, the present invention can be applied to simplify the configuration of the fuzzy inference engine, and thus the present invention can be extremely usefully used for constructing a fuzzy red computer.

Description of examples 1. Fuzzy inference The simplest human rule of thumb.

"If X is A, then y is B"(If' x is A, then y is
B) can be expressed as a metal. here.

“If X is A” is the antecedent part (antcccdcnt
).

"y is B" is called a consequent. A and B are ``tall'' and ``people with nicknames.''

Ambiguous linguistic information such as "a small positive value" can be characterized by the fuzzy membership function as described above. That is, A
, B are fuzzy sets (in the specific circuit description to be described later, A, B, etc. indicate a fuzzy membership function or a voltage distribution representing the fuzzy membership function).

The above metals are easily x+wA → y-B It is expressed as

Humans often make inferences that include fuzzy expressions in the antecedent and consequent parts. This quib inference cannot be performed satisfactorily using classical pool logic.

Consider the following form of reasoning.

Implication: x
-A -* y -B premise (prcaisc) N -A- conclusion (eonclusion): y''B゛This form of inference, i.e. inferring a conclusion from a given premise when an implication exists, is `` - generalized modus ponens
modus ponens) J. Implications are also called major premises, and premises are also called minor premises or premises.

There may be multiple implication rules, as shown below.

Implication 1: X”A-*yssBelse or and Implication 2: x-A −+ym13 else or and Implication r: otherwise) or and (and).

There is also the following form of reasoning.

Implications: x-A → y-B
Mistake: ysm
B - Conclusion: x-A-
This form of reasoning is -membraned modus torrent (m
It is called odus tollens).

A fuzzy computer basically consists of a fuzzy memory that stores the above-mentioned implication Q rules,
It consists of a fuzzy inference engine that executes Modus Ponens fuzzy inference.

Let's further analyze the fuzzy reasoning of Modus Ponens.

"fuzzy relation from A to B"
ionf'rom A to B) J, and this is expressed as RAB (hereinafter simply abbreviated as R).

Generally A-(a,a,...,a,...la)1
2 1 ■ B-(b , b , ..., b9. ..., b
112 J n , the fuzzy relation R from A to B is expressed as.

Various operations have been proposed to express this fuzzy relationship.

For details, see Masaharu Mizu II loto a.
nd Irans-Jurgen ZlamerfIl
ann, -Comparison of' Fuzz
yReasoning Methods,” Fuzz
y 5ets and Systems Vol, 8.
No, 3. pp, 253-283. (1982).

Typical fuzzy relationships that have already been proposed include the following.

r tj"" a tΔbj MIN operation rule r - (a Ab-)V (1-a,) MA
X rule Ij i J r −1△(1a r Ab J ) Arithmetic rule + j The MIN arithmetic rule expressed by equation (1) is the most well-known, and its effectiveness has been proven in industrial applications. Therefore, in this embodiment, the calculation rule of equation (1) is adopted. however.

It goes without saying that many other calculation rules are also applicable.

As mentioned above, one implication rule (x
-A-ey-B), when a blemise (x”A') is given, the inference composition rule (composltlon) is used to infer a conclusion (Y -B') from these.
(al rule of'Inl'erence) J is expressed using the fuzzy relation R as follows.

B"-A-+eR = [a', a2', -, a,'
, -, a' ko1 m Various operations have been proposed for the operation of * in the above equation. For example, the method uses M I N/MAX operation 2 algebraic product/MAX operation. In this embodiment, the most commonly used M I N/MAX operation is used as the * operation.

Therefore, the conclusion according to the rules of inferential composition is, is.

When the M I N/MAX operation is used as the main operation and the equation (1) is used as the fuzzy relationship, it is expressed as quadratic.

b,'-(a “△r ,)v(a2゛△r2j)
■・・・J l lJ v (B1°△r1j)■・・・v(affi′△r
, j) The calculations in equation (2), equation (3), or equation (4) are executed by the fuzzy inference engine, which is the main part of the fuzzy combination, as described above.

From these formulas, the fuzzy inference engine calculates MI to the main crab.
It will be understood that it is comprised of an N circuit and a MAX circuit.

Therefore, before describing the configuration of the fuzzy inference engine, the MIN circuit, MAN circuit, and other basic circuits will be explained. Analog electrical signals that indicate the value (grade) of the membership function include voltage signals and current signals.

In the following, we will discuss a circuit operating in the QjE mode as an example.

2. MIN circuit, MAX circuit and other basic circuits (1) MIN circuit, MAX circuit n input 1 constructed using bipolar transistors
An example of an output MIN circuit is shown in FIG. 1(A). The input voltages are X t , X 2 , . . .

xn and the output voltage is 2, this circuit performs the calculation of Z-AXl. That is, it generates an output voltage equal to the lowest input voltage.

This MIN circuit is composed of a comparator (comparison circuit) and a convencator (compensation circuit). The comparator consists of n P N P whose emitters are coupled to each other.
l-transistor Q, Q, Qll 12
13...''In, and a transistor Q1 as a current source that drives these transistors.The input voltage X-X is applied to the bases of the transistors Q11 to nQln, respectively.The transistor Q
A reference voltage φ1 is applied to the base of the transistor Ql so that a predetermined constant current flows through the transistor Ql. The lowest input terminal (V
Since the transistor with l1In applied to its base becomes conductive, the other transistors become cut-off. Therefore, a voltage that is the sum of the input voltage V and the emitter/base voltage of the transistor m1 in a conductive state plus VEB appears at the emitter, that is, V+V,B-[F]x1+1n (VEB is about 0.7V). '. If the two input B input voltages are equal and lower than the other input voltages, the two input voltages will cause the input transistor to
/2 current flows, so the result is the same. The same applies when three or more input voltages are equal and lower than the other input terminals.

The convencator compensates for the voltage VEB appearing as a MIN calculation error in the output of the comparator. This convencator is composed of an NPN transistor Q and a transistor Q3 which serves as a current source to drive current to this transistor Q2. A voltage φ2 necessary for causing a constant current I2 to flow is applied to the base of the transistor Q3. The emitter of transistor Q2 is connected to the output terminal of this MIN circuit. As a result of subtracting the base/emitter voltage VBE of transistor Q2 from the output voltage of the comparator, the output voltage 2 is G
It will represent X s.

The transistors Q 1 and Q 2 acting as current sources can also be replaced with resistors. Also, the emitter is the power supply ■cc
A new PNP (PNP) transistor connected to the transistor Q1 is newly provided, and this transistor and the transistor Q1 form a current mirror. Then, by adjusting the resistor connected in series with the newly installed transistor, the desired current 1
1 can also be made to flow.

FIG. 1(B) shows an improved MIN circuit. Components in this circuit that are the same as those shown in FIG. 1(A) are given the same reference numerals.

In the MIN circuit of FIG. 1(A), transistor Q1
, ~V of Q1n. B is not necessarily the same value, but considering transistor Q11 as its representative, let us assume that V
shall be. Let BI 2 of transistor Q2 be V. BE by convencator
BE2 The error in the MIN operation is completely compensated for by V
−■ It is when. That is, TrabiBi
BE2 VEB where transistors Q1, ~Q1n and Q2 are exactly the same
-IE (or ■BE-IE), the error will be 0 when I ” I 2.
In order to obtain I''I2 in the circuit shown in FIG. 2A, voltages φ and φ2 must be adjusted.

(2) In the improved circuit shown in FIG. 1(B), a transistor Q4 is provided in series with the transistor Q2, and a current mirror is formed by this transistor Q4 and the transistor Q1.

If a constant current I2 is caused to flow through the transistor Q2, a current 11 which becomes 1l-I2- will also flow through the transistor Ql, and there is no need to adjust the voltages φ1° and φ2. Furthermore, a transistor Q3 as a current source and a transistor Q5 forming a current mirror are provided, and this transistor Q5 is connected to Io
If driven by a current source, the current will always be I2-Io. In other words, a constant current can always flow regardless of variations in the power supply voltages V and -VEE, resulting in a circuit that is extremely resistant to variations in the power supply voltage. Also transistor Q6 as a current source for the other MIN circuit. By forming a current mirror with transistor Q5, one current source IO
It becomes possible to drive with

However, this improvement has an H effect when extremely strict calculations are considered, but later the Chondral MI N-MA
As described in the X circuit, even if the currents 11 and 12 are different, it does not make any difference in practical terms.

FIG. 2 shows an example of an M A X circuit. This M
The AX circuit also consists of a comparator and a compensator. The comparator has input voltages X and X
, ..., base controlled by X12
n and whose emitters are interconnected NPN transistors Q
, Q 2 , . . . , Q2n, and a transistor Q7 for driving these transistors with current. Of the transistors Q21 to Q2n, only the transistor to which aX is applied to the highest input terminal (denoted as V) becomes conductive, and a voltage of V - V nE appears at its emitter. As a result of this error of -la
, x output voltage 2 is obtained. This ff1aX
It goes without saying that the n MAX circuit can also be improved according to the concept shown in FIG. 1(B).

In these MIN circuits and MAX circuits, the input terminal
−Xs represents a fuzzy truth value (multi-value [grade] of membership function). Fuzzy truth values take continuous values [0, 1] from 0 to 1. Correspondingly, the input voltage is.

For example, it is set to [OV, 5V].

Since all the transistors in the comparators of the MIN circuit and MAX circuit described above are mutually coupled at the emitter, this circuit is named an emitter-coupled fuzzy logic gate (ECFL gate).

The MIN and MAX circuits described above can be thought of as a cascade of two emitter floors driven by current sources (transistors Q 1 , Q 2 , Q 2 , QB). Therefore, they exhibit very high input impedance and very low output impedance. This fact is.

This shows that these circuits are resistant to external noise and signal crosstalk, which means that many circuits can be connected to subsequent stages.

Further, since the above-mentioned MIN circuit and MAX circuit are driven by a current source, saturation does not occur in each transistor. That is, the accumulation effect of minority carriers in the base region does not occur. therefore.

These circuits exhibit very fast computational speeds. According to experiments, the response speed was 10 nsec or less.

Furthermore, the input/output static characteristics of the entire nine circuits are not affected by opening one or some of the input terminals of the circuits described above. This is very important for building large-scale systems.

Furthermore, in the above-described circuit, it is also possible to replace the PNP and NPN transistors with p-channel and n-channel MOSFETs, respectively.

The above applies not only to the above-mentioned MEN circuit and MAX circuit, but also to all the circuits described below.

(2) In the classification method of M I N circuits and MAX circuits, MI
In addition to considering the developed forms of the N circuit and MAX circuit, for the convenience of explaining the circuits that constitute the fuzzy inference engine, these are classified into several forms.

In the MIN circuit shown in FIG. 1, two inputs X,
In order to consider only X, transistors Q13 to Q1n for other inputs are omitted. Also input x1. Let x2 be X and y, respectively. Then this MIN circuit becomes Z”XA
This is a 2-input, 1-output MIN circuit that calculates y. If you prepare n MIN circuits with 2 inputs and 1 output like this,
As shown in Figure 3(A), 2n inputs (x, x
2.・.

xo, yl, y2. ..., y)n output (zl.

Z2+..., 2) becomes a MIN circuit. In this circuit, one output 2 is obtained as Z -X A)' by corresponding inputs X and yI. Therefore, this type of MIN circuit will be referred to as a corresponding MIN circuit (abbreviated as C-MIN). Do the same.

The 2n-input n-output MAX [i path that performs the MAX operation of zl-xlvyl (i -1 to n) is called a Cores bonding MAX circuit (abbreviated as C-MAX).

C-MIN and C-MAX are symbolized as shown in FIG. 3(B). Thick arrows similar to bus symbols represent n signal lines. The n written inside this arrow indicates the number of signal lines. Fuzzy membership function X.

n multi-values of Y are expressed as voltages distributed on each signal line. Therefore, C-MIN.

C-MAX is the MIN of two membership functions x, y
It can be said that they are circuits for performing calculations and MAX calculations, respectively. Voltages representing n multi-values of the membership function 2 generated by the calculation also appear as a distribution on the n signal lines.

In contrast to C-MIN, C-MAX mentioned above.

The n-input 1-output MIN circuit shown in Figures 1 and 2, M
Since the AX circuit outputs the result of unsampling the n input signals, it is called an unsampling MIN circuit or an unsampling MAX circuit (abbreviated as E-MIN or E-MAX). These circuits are shown simplified as shown in FIG. 4(A) and symbolized as shown in FIG. 4(B).

Furthermore, we will propose another special MIN circuit.

It is a Cartesian product (or Cartesian product) MIN circuit that performs the "fuzzy relation from A to B" described above.
slan product MIN clrcuit:
(abbreviated as CP-MIN). As shown in equation (1), this embodiment employs the MIN operation rule as an operation expressing the fuzzy relationship.

This CP-MIN is.

A-ta,,a2. -, a , -, a 11
ta B-(b, b,..., b,,..., b 11
2 J n as input, fuzzy relation R-[r, r, ..., ",, ..., rko1 2
3 n r 1:, ``'' This is a circuit that outputs a + A b j.

The symbol of CP-MIN is shown in FIG. 5(A), and a simplified circuit is shown in FIG. 5(B). And the fifth
An example of a circuit symbolized in FIG. 6 as a crossover of a, b, and rsj lines is shown in FIG. The circuit in FIG. 6 is a MIN circuit in which transistors Q13 to Q1nG of the MIN circuit in FIG. 1 are omitted and the circuit is modified to have two inputs. In FIG. 6, the same components as those shown in FIG. 1 are given the same reference numerals.

(3) Truncation circuit The truncation circuit cuts the two-input membership function X at a certain value a, as shown in Figure 7.
The membership function X' obtained as a result of this cutting is output. This circuit is used to build a fuzzy inference engine using MIN, MAX operations, as shown below. The truncation circuit has n inputs, one truncation input a and n outputs.

A specific example of the truncation circuit is shown in FIG. The n inputs representing the fuzzy membership function X are Xl, X2+...,X, and the truncated output fuzzy φ membership function
. . , each expressed in x ° 1 x 2
n It is. This circuit converts the MIN circuit of the two-person car output into n
(i.e., C-MIN), and connect one input of each MIN to each other to create a truncating input a.
It can be said that It can also be said that it is composed of a truncator and a convencator.

(4) MI N/MAX circuit Cascade connection of MIN circuit and MAX circuit.

It is often used to construct fuzzy inference engines, which will be described later. FIG. 9 shows an example of such a cascade connection. In FIG. 9(A), the output sides of the 1 m input E-MIN and the n input E-MIH are connected to the input side of a 2 input MAX circuit.

Figure 9 (I3) shows 1m input E-MAX and n input E-MAX.
A circuit is shown in which a 2-input MIN circuit is connected after -MAX. Examples of cascade connections between NIN circuits and MAX circuits are not limited to these, but include cascade connections between C-MIN and E-MAX, connections between multiple E-MINs and E-MAX installed in parallel, etc. Conceivable.

FIG. 1O shows an embodiment of the circuit shown in FIG. 9(A) using the specific MIN circuit and MAX circuit shown in FIGS. 1(A) and 2. One E-M
The symbols shown in FIG. 1(A) and FIG. 2 are used for the constituent elements of the IN and MAX circuits. However, the transistor Q is given a Ql- symbol. In addition, in the other E-MIH, a dash is added to the symbol of the corresponding element of one E-MIN. Transistor Q1
The transistor corresponding to 01 is labeled Q°.

n In FIG. 10, the EMIN compensator (transistor Q2) compensates for the positive voltage shift at the emitter junction of the preceding comparator, as described above. Furthermore, the convencator (transistor Q9) in the two-input MAX circuit compensates for the negative voltage shift at the emitter junction of the preceding comparator.

Since the E-MIN convencator and the MAX circuit convencator compensate for voltage shifts in opposite directions, there is no change in the value of the final output 2 even if these convencators are omitted.

A circuit constructed based on this idea by omitting the two-car compensator is shown in FIG.

A comparison with the circuit of FIG. 1O will show that the circuit of FIG. 11 is extremely simplified. This saves transistors, increases operating speed, and reduces power consumption. This compensator omission technique.

Needless to say, it can be used in a cascade connection between a MAX circuit and a MIN circuit or a cascade connection between a truncation circuit and a MAX circuit.

(5) Condrol MIN-MAX circuit The chondral MIN-MAX circuit is a circuit that works as a MIN circuit or a MAX circuit depending on the control input, and an example thereof is shown in FIG. This circuit has two signal inputs x, y, one control input C and one output 2.

The circuit of FIG. 12 is based on the E-MIN transistors Q12 to Q1°Q° in the MIN-MAX circuit of FIG.
It is constructed by omitting ˜Q′. Signal inputs X+V are applied to the bases of transistors Q 1 and Q', respectively.

Furthermore, an analog switch controlled by a control input C is connected between the emitters of transistors Q 1 and Q 2 . This analog switch consists of a pair of n-channel and p-channel MO3FETs connected in parallel.
Q and Q32, and FETQ3.
The control input C is directly applied to the gate of FET Q32, and the control input C is inverted by an inverter and applied to the gate of FET Q32.

Control input C takes binary high values, that is, H level (for example, 5V) and L level (for example, OV). When control input C is at L level, the analog switch is turned off. In this case, the circuit of FIG.
It is the same as the 12 1 m 12 in circuit obtained by removing the transistors Q-Q, Q'~Q ° from the circuit shown in the figure, so 2-(△x) V (△y)"
The output of xvy is obtained (△X, △y are equal to x, y,
Although it has no meaning as an arithmetic operation, it works as a MAX circuit (expressed in this way based on the analogy with FIG. 11). When the control input C is at H level, the analog switching circuit is turned on, transistors Q and Q' act as comparators, and one of transistors Q and Q acts as a convencator, so it becomes a MIN circuit (the first
(Compare with the circuit in figure (A)). At this time, since there are two current sources Q, Q, and ', the additional current from both types of current sources Q and Q' flows to the transistor Q and Q' that is in a conductive state. . Therefore, the voltage shift at the emitter junction of the transistor in the quadruple state becomes somewhat large, and a slight error occurs in the compensation by the convencator. However, this error hardly poses a problem in practice. This is because the vEB-IE characteristic of the transistor has an extremely steep rise. According to experiments, when the emitter current force is 5 mAJ), V EBl;i 0.71
When V, 10IA(7), vEB was 0.725V. Therefore, even if the emitter current In is doubled, only a difference of 0.015 V will appear in IEB. If the signal input X or y varies in the range of 0 to 5 V (fuzzy truth value θ ~ 1), 0
．． 015V is a completely negligible value.

3. Fuzzy Inference Engine (1) Basic Inference Engine The fuzzy inference engine, which is a unit that executes the Modus-Bonens fuzzy inference mentioned above, will be described.

First, we will explain a basic inference engine that performs a simple inference that includes only one fuzzy proposition (``If X is A: x=AJ'' mentioned above) in the antecedent part of an implication, and We describe an extended fuzzy inference engine (extended inference engine) that performs inference.

The concept of a basic fuzzy inference engine that performs simple inference is shown in FIG. This inference engine is
It inputs the fuzzy dispute membership functions A, B, and A' corresponding to the fuzzy proposition given based on the above-mentioned fuzzy inference synthesis rules, and outputs the fuzzy membership function B'' representing the conclusion. These fuzzy membership functions A, B, A'' and B'' are realized by analog voltages distributed on m or n signal lines corresponding to the elements of the fuzzy set.

The basic fuzzy inference engine is a circuit that executes the calculation of equation (2), equation (3), or equation (4) described above. At least three types of fuzzy inference engine configurations are possible corresponding to equations (2), (3), and (4), and these are designated as types [1], [2], and [3].

(2) Type [1] The basic fuzzy inference engine of type [1] is
), and a block diagram thereof is shown in FIG. A voltage input representing a fuzzy membership function A distributed over m signal lines and n
A voltage input representing a fuzzy membership function B distributed on the main signal line is given to CP-MINII, where nXm output voltage signals (r, , j- 1 to n) are obtained. n C-MIN12 are provided, and each C-MIN12
A signal (m
A set of n voltage signals) and a signal r j (r j is composed of n voltage signals) representing the result of the above CP-MIN calculation are respectively provided. The output of each C-MIN 12 consists of m voltage signals representing a Ar1j (i-1 to n). Further, n E-MAX 13 are provided, and each E-MAX 13 performs MAX calculation of m voltage signals inputted thereto. Therefore, n E-M
A fuzzy membership function B'' can be obtained which represents the conclusion as a set of analog voltages S,° distributed on the n output signal lines of the AX13.

In the cascade connection of C-MIN 12 and E-MAX 13, it is possible to omit the compensator as described above.

(3) Type [2] The basic fuzzy inference engine of type [2] is
), and a part of its block diagram is shown in FIG. All j(j””1～
It is necessary to perform the calculation of a1°ΔalAbj (i-1 to m) for n). Therefore, m E-MINs 21 are provided for each value of j, and voltage signals of a', a (im1 to m) are input to each E-MIN 21. A total of nXm E-MINs are required. For each value of j, m outputs of m E-MIN21 are E-MAX
Sent to 22nd. n E-MAX circuits 22 are provided, and the output voltage from each E-MAX 22 is S,'(j-1
~n) is obtained.

Also in this circuit, the convencator can be omitted in the cascade connection between E-MIN 21 and E-MAX 22.

FIG. 16 shows a specific route configuration for obtaining one of the blocks (specifically, b1') in the block diagram shown in FIG. 15. In E-MIN21 and E-MAX22, the same parts as shown in FIG. 1(A) and FIG. 2 are given the same reference numerals.

Its structure can be easily understood. E-MIN
A multi-output current mirror is constituted by the transistor Q1 which acts as a current source of 21 and the newly provided transistor Q33, and the transistor Q acts as a current source 1.
1. Therefore, all E-MINs 21 can be driven with the same current with a simple configuration. Similarly, the transistor Q7 as a current source of the E-MAX 22 constitutes a current mirror with the newly provided transistor Q34, and is driven by the current source 112.

(4) Type [3] The basic fuzzy inference engine of type [3] is
), and its block diagram is shown in FIG. Voltages representing fuzzy membership functions A, A- distributed on m signal lines, respectively, are applied to C-MAX 31, where at゛Δa
1 (iml~m) MIN calculation is performed. That m
These output voltages are input to E-MAX32. This E-M
AX flight.

The output of 22 represents VaAa, and the truncate also...
1 is given to the truncation circuit 33 as a ting input a. On the other hand, the truncation circuit 33 has a fuzzy membership function B distributed on n signal lines.
The voltages (b, , j-1 to kn) representing the values are input. In the end, the truncation circuit 33
Then, the calculation of equation (4) is performed, and a conclusion B' can be obtained as a result of the analog voltages distributed on the n output lines.

A specific electronic circuit of this type [3] fuzzy inference engine is shown in FIG. In these figures, elements corresponding to those shown in FIG. 1(^), FIG. 2, FIG. 8, and FIG. 16 are given the same reference numerals. C
- A compensator is omitted in the cascade connection of MIN31 and E-MAX32. The truncation circuit 33 is exactly the same as that shown in FIG. C-M
Transistor Q1 as m current sources of IN31 is
Together with the transistor Q1 of the truncation circuit 33.

It constitutes a multi-output current mirror with transistor Q33. Transistor Q7 as a current source in E-MAX32 forms a seven-output current mirror with transistor Q34 together with transistor Q of truncation circuit 33.

The type [3] inference engine has a much simpler configuration than the other types [11 and [2] inference engines. This type [3] inference engine has the following characteristics except for the transistor QQ.

It is composed of 3B' 34 (4m+5n+l) transistors. Rather than in the form of a monolithic IC.

Experiments using discrete bipolar transistors have yielded operational speeds of 100 nsec (10-7 sec). This means that this basic inference engine does exactly to, ooo per second. This means that fuzzy inference can be realized 000 times (10Mega FIP
S: PIPS = Fuzzy Inference
s Per 5 seconds).

(5) Extended inference engine As shown below, inferences that include two fuzzy propositions in the antecedent part of an implication may be necessary. This is called extended fuzzy inference. The antecedent of an implication is “and/or”
They are joined by J.

Either "and J" or "or J" is selected.

Implications: If X is A and/or y is B, then 2 is C (II' x 1s A andlor y ls
B, then zi is C) Blemish: X is A′ and/or y is Bo Conclusion: 2 is C′.

The implication of this is expressed symbolically as follows: x = A andlor y m B −b z m
C press mistake: x-A'' andlor y -
B' Conclusion: z-C- This extended fuzzy inference is performed by an extended fuzzy inference engine. The concept of an extended inference engine is shown in FIG. The inputs are the fuzzy fist membership functions A, B, C, A- and B=, and the combination selection C to select the "and/or" combination. The output is a fuzzy fist membership function C- representing the conclusion.

The fuzzy membership functions A, A- are due to the voltages distributed on m signal lines, and B, B= are due to the voltages distributed on m'' signal lines.

C is represented by voltages distributed on 11 signal lines.

FIG. 20 shows the configuration of this expanded inference engine, which is obtained by slightly modifying the configuration of the basic inference engine of type [3] shown in FIG. 17. Fuzzy Mempage 1. Between the functions A and A′, C
-MIN calculation is performed (C-MIN31A),
E-MAX calculations of m voltages representing the results are performed (E-MAX 32 people). C-MIN and E-MAX calculations are also performed for fuzzy membership functions B and Bo (C-MIN31B, E-MAX32B
). The combination "and" is realized by the MIN operation in this embodiment, and "or" is realized by the MAX operation. In order to easily perform the operation and selection of this combination, the above-mentioned condolence MIN -MA
An X circuit 34 is used. The two E-MAX calculation results are input to this condord MIN-MAX circuit 34. Then, a combination selection input signal C for selecting "and" or "or" is applied as a control input to the condrol MIN-MAX circuit 34. The fuzzy membership function C is given to the truncation circuit 83, and the truncation signal is the chondral cord M.
The output a of the IN-MAX circuit 34 is given. The truncation circuit 33 provides the voltage distribution of the fuzzy membership function representing the conclusion C'.

[Brief explanation of the drawing]

FIG. 1(A) is a circuit diagram showing an example of an n-input, one-output NIN circuit, and FIG. 1(B) is a circuit diagram showing an improved type thereof. FIG. 2 is a circuit diagram showing an n-input 1-output MAX circuit. Figures 3 to 6 show the classification of MIN circuits or MAX circuits, and Figure 3 (A) shows the Cores bonding MI circuit.
N (C-MIN) or cores bonding MAX
(C-MAX), Figure 3 (B) shows its symbols, and Figure 4 (A) shows the unsample MIN (E
-MIN) or ensample MAX (E-MAX)
Figure 4 (B) shows the concept of
P-MIN), FIG. 5(B) shows a simplified circuit thereof, and FIG. 6 shows a specific example of the circuit symbolized as a line crossing in FIG. 5(B). It is a diagram. FIG. 7 shows the concept of a truncation circuit. FIG. 8 is a circuit diagram showing a specific example of the truncation circuit. FIGS. 9(A) and (Il) are block diagrams showing the cascade connection of the NIN circuit and MAX circuit, respectively. FIG. 10 is a circuit diagram showing a specific example of the circuit in FIG. 9(A). FIG. 10 is a circuit diagram showing a circuit in which the compensator of the circuit of FIG. 10 is omitted. FIG. FIG. 12 is a circuit diagram showing a condorade MIN-MAX circuit. FIG. 13 shows the concept of a basic fuzzy inference engine. FIG. 14 is a block diagram showing the configuration of a type [1] fuzzy inference engine. FIG. 15 is a block diagram showing part of the configuration of a type [2] fuzzy inference engine, and FIG. 16 is a circuit diagram showing its specific circuit. FIG. 17 is a block diagram showing the configuration of a type [3] fuzzy inference engine, and FIG. 18 is a circuit diagram showing its specific circuit. FIG. 19 shows the concept of an extended fuzzy inference engine, and FIG. 20 is a block diagram showing an example of its configuration. Q , Q , ..., Ql, ... MIN circuit transistor. Q', Q',...,Q ゛...11 12 in transistor of MAX circuit. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Kenji Ushiku (and 1 other person) 3rd (A) 41st (A) 2■Vx+ Figure (B) Figure 5ri "QtAt)j ・Taken> CS = 〉 Then ε≦Latitude i is Fig. 17 B' Fig. 19 Fig. 20

Claims (1)

[Scope of Claims] A plurality of three-terminal control elements whose control terminals are each given an input and whose carrier injection terminals are commonly coupled to serve as an output terminal are arranged such that the three-terminal control element to which the smallest input is given is conductive. A comparator for MIN operation that is connected to the state of A MIN/MAX circuit in which a 3-terminal control element to which an input is applied is connected in a cascade to a comparator for MAX calculation, which is connected so that it is in a conductive state.