JPS63133003A - Length/speed measuring apparatus - Google Patents

Abstract

PURPOSE:To enable accurate count processing in real time, by calculating the length and distance of an object with a calculating section depending on the comparison of counts with a reference count value set for a reference value setting section each time the detection of a correlation peak is performed. CONSTITUTION:When a laser light of a light projecting/receiving system 11 irradiates a moving object, speckle patterns are generated by the scattered lights thereof and signals thereof are received with receivers. A correlation peak is detected with a peak detecting section 27 at a timing of a specified clock signal between signals received with the receivers and based on the results of peak detection, the number of clocks equivalent to a specified length of a moving object is set with a reference setting counter 53 as reference count value. A counting section 14 compares to calculate counts obtained by a clock counting counter 52 with a set reference calculated value set for the reference setting counter 53 to the length and speed of the moving object.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for measuring the length and displacement (hereinafter simply referred to as "length") of a moving object, as well as its speed, in a non-contact manner. -Relating to a speed measuring device.

<Prior Art> As a conventional device of this type, there is a measurement device that utilizes a speckle pattern.

FIG. 15 shows the principle, in which a laser beam 1 is irradiated onto an object 2 moving at a speed of {circumflex over (2)}. The reflected light from the object 2 is scattered and spread in space, and due to the coherence of the laser beam 1, this scattered light becomes a speckle pattern with clear brightness and darkness. This speckle pattern moves simultaneously with the movement of the object 2, and this moving speckle pattern is aligned along the moving direction. It is detected in each second photoreceiver 3.4.

Each light receiver 3.4 converts the received light signal into an analog electrical quantity, and this electrical signal is binarized by a comparison circuit to become a binary signal. In this case, the binary signal obtained by the second light receiver 4 (hereinafter referred to as a "delayed signal") is transmitted to the first light receiver 3.
It is detected with a delay of a certain delay time τ4 with respect to the binary signal obtained by (hereinafter referred to as "preceding signal").

Thus, as shown in FIG. 16, N1 bits of the leading signal are taken into the memory 5, and N2 bits of the delayed signal (where Hz > N) are taken into the other memory 6 simultaneously at a certain sampling period T. After that, the match determining circuit 7 compares each bit data of the preceding signal with each predetermined bit data of the delayed signal to determine whether the data contents match or do not match.

In this case, first, it is determined whether the data of the 1st to N1th bits of the preceding signal match the data of the 1st to N1th bits of the delayed signal. As a result, by counting the number of bits whose data contents match with each other using a counter 8, a negative degree (correlation degree) X can be obtained. This value X means the correlation value when the time shift of the memory 6 is zero (indicated by K=O in the figure).

Next, the 1st to Nth bit data of memory 5 and memory 6
A match is determined between the 2nd to (N++1)th bit data of It is determined by

Similarly, the time shift is TXj (however, j・0,
1, 2. ...), and as a result, a correlation curve 9 having a correlation peak P as shown in FIG. 17 is obtained. Then, the delay time τ to the correlation peak P is obtained from this correlation curve 9. For example, by substituting this delay time τ4 into the following equation 0, the velocity V of the object 2 is calculated, and further, this velocity V is expressed as the time The length and displacement (traveling distance) of the object 2 are calculated by integrating with .

τd In the above formula, X6 is the distance between the light receivers 3.4.

k is a constant.

<Problems to be Solved by the Invention> However, in the case of the above method, data input is prohibited after the necessary amount of data for the leading signal and the delayed signal is loaded into the memories 5 and 6, and correlation processing is performed by the memory drive. However, there is a problem in that it takes time to detect the correlation peak and, in turn, measure the length and velocity of the object, making high-speed processing in real time particularly difficult.

This invention is intended to solve the above problem,
The purpose of this invention is to shorten the time required to detect the length and velocity of a moving object and to provide a novel length/velocity measuring device that enables real-time measurement processing.

Means for Solving the Problems In order to achieve the above object, the present invention includes a projector for irradiating light onto a moving object, and a projector disposed at a predetermined distance for receiving light scattered on the surface of the object. The first A variable clock generator that generates a clock signal by determining the clock frequency so that the delay time of the light reception signal by the second light receiver relative to the light reception signal by the first light receiver and the light reception signal by the first light receiver is a constant value in terms of the number of clocks. a clock counting section for counting the clock signal; 1. A peak detection section for detecting a correlation peak at an arbitrary clock signal timing between the light reception signals by the second light receiver; - a reference value setting section for setting the number of ticks as a counting reference value; and a length/velocity of the moving object based on a comparison between the count value of the clock counting section and the counting reference value set in the reference value setting section. A length/velocity measurement device was constructed with a calculation section for calculating the .

Effect> When a moving object is irradiated with laser light, a speckle pattern is generated by the scattered light, and the signal is transmitted as the first signal.
The light is received by each second light receiver.

These light reception signals are binarized, but the light reception signal from the second light receiver is delayed by a certain delay time with respect to the light reception signal from the first light receiver.

The variable clock generating section determines the clock frequency so that this delay time becomes a constant value in terms of the number of clocks, and generates a clock signal. This clock signal is given to a clock counting section and the number of clocks is counted.

On the other hand, in the peak detection section, the first. A correlation peak is detected at the timing of a predetermined clock signal between the light reception signals by each of the second light receivers, and based on the peak detection result, the number of clocks corresponding to the predetermined length of the moving object is set as a counting reference value by the reference value setting section. is set to

In this manner, the calculation section compares the counted value by the clock counting section with the counting reference value set in the reference value setting section, and calculates the length and speed of the moving object based on the comparison operation.

According to the present invention, measurement processing can be performed in real time, and the time required to measure length and speed can be significantly shortened compared to conventional examples.

<Embodiment> FIG. 1 shows an example of the overall schematic configuration of a length/velocity measuring device according to an embodiment of the present invention. Signal processing section 12. It is composed of a polarity correlator 13 and a counting section 14.

As shown in FIG. 2, the light projecting/receiving system 11 has a light source composed of a semiconductor laser 15, and the output power of the semiconductor laser 15 is stabilized by an automatic power control circuit (APC circuit) 16. The beam emitted from this semiconductor laser 15 is collimated by an optical system 17, and the moving object 1
8 is irradiated. This irradiated light is scattered on the surface of the object 18, and the reflected light generates a speckle pattern due to the coherence of the laser light. This speckle pattern is the first. Each of the second light receivers 19 and 20 receives and photoelectrically converts the light, and the electrical signal is sent to the signal processing section 12. The light receivers 19 and 20 are arranged along the moving direction of the object 18 at a predetermined interval X4 equal to or larger than the average speckle size.

The signal processing section 12 includes a pair of comparison circuits for discriminating and binarizing the light reception signals from each light receiver 19, 20 at a predetermined level.

FIG. 3 shows a concrete circuit example of these comparison circuits 21, and FIG. 4 shows signal waveforms of each part of the circuit.

In FIG. 3, the preamplifier circuit 22 receives the output signal A from the photoreceiver.
is amplified, and the amplified output is subjected to a DC component removal circuit 23 in which the DC component is captured.

The output B of this DC component removal circuit 23 is given to a Schmitt trigger circuit 24, where it is discriminated based on a Schmitt level set near zero level and is converted into binary outputs CI, C.
2 is generated. The binary output C2 of the second optical receiver 20 is delayed by a certain delay time τ4 with respect to the binary output C1 of the first optical receiver 19, and one binary output C3 is used as a preceding signal and the other The binarized output C2 of is a delayed signal,
Each signal is applied to a polarity correlator 13.

Returning to FIG. 1, the polarity correlator 13 includes a variable clock generator 25. Shifter section 26. The configuration includes a peak detection section 27 and a decoder section 28, and specific configuration examples thereof are shown in FIGS. 5 and 6.

In FIG. 6, 29 is a speckle signal obtained by each of the light receivers 19 and 20 (corresponding to A in FIG. 3), and 30 is a binary signal generated by the comparison circuit 21 (see FIG. 3). 31 is a data string taken into the shifter section 26 of the polarity correlator 13, and 32 is a clock signal CK generated by the variable clock generation section 25 of the polarity correlator 13.

The shifter section 26 includes a pair of shift registers 33 and 34.
The first shift register 33 contains a binary data string of the preceding signal, and the second shift register 34 contains a binary data string of a delayed signal having a certain time delay τ4 with respect to the preceding signal. They are input in series at the same time.

Each shift register 33 and 34 has a variable clock generator 2.
The binary data of Nt bits (N, = 1.02 in FIG. 6) is transferred to the first shift register 33 and transferred to the second shift register 34. is Nt (Nz < N
t ) bits (N, = 6 in FIG. 6) of binary data are respectively taken in.

Although the details will be described later, the variable clock generating section 25 adjusts the frequency fcK of the clock signal CK so that the delay time τ becomes a constant value (for example, 100 clocks).
is set variably.

FIG. 7(1) shows the relationship between the respective shift registers 33, 34, in which the configuration data AI+AZ+... of the preceding signal is sequentially input in series to the first shift register 33, while the A delayed signal is serially inputted into the shift register 34 after being delayed by a delay time τ4 corresponding to KP in terms of the number of clocks with respect to the preceding signal. Note that the delay time τ4 is theoretically calculated as τ,=T×, where T is the period of the clock signal GK.
Becomes KP.

The first shift register 33 serially outputs the captured binary data, and the second shift register 34 outputs the captured binary data in parallel. The data and all the bits of data related to the parallel output of the second shift register 34 are provided to the success/defeat determining section 35 of the peak detecting section 27 to determine whether the data match or do not match.

Note that the coincidence determination section 35 is configured using, for example, an exclusive NOR circuit.

FIG. 7(2) shows the discrimination operation of the coincidence discrimination section 35, in which the first shift register 33 has the constituent data of the preceding signal 5, 1 to AM9, and the second shift register 34 contains the configuration data A of the delayed signal (i + N, -, 1
10N and -1 are respectively taken into -(N, -+)ゞ. In addition, the match determining unit 35 includes the final bit data A serially output from the first shift register 33;
However, all bits of data output in parallel from the second shift register 34 (center H jini p) - (Nl- edition)
P is given to each of A'A i+N+-, and a match in data content is determined between these data.

This first. When one clock signal CK is applied to each of the second shift registers 33 and 34, each shift register 33
．． 34 performs a shift operation by one bit and shifts to the state shown in FIG.
The following parallel output data A from the shift register 34 of
(i+N, -Kp)-(Nyo-I,+1~A t"
Nl −Kp + 1 are given, respectively.

The determination result of the coincidence determination section 35 is given to the peak detection section 27 including a counter group 36, and the second shift register 3
The degree of coincidence for each bit of 4 is counted by a plurality of counters (N2) counters 37A to 37X (shown in FIG. 11) constituting the counter group 36, respectively.

In FIG. 7 (21(3)), the counting results by this counter group 36 are shown on orthogonal coordinates.The orthogonal coordinates are plotted on the horizontal axis as each bit position of the second shift register 34 (the time shift l- (corresponding to
The number of losses (indicated by diagonal lines in the figure) is accumulated at the position of KP within the range of .

Figure 8+11 to (3) are shown in the above 1. A specific configuration example of each of the second shift registers 33 and 34 and the coincidence determination unit 35 is as follows.
This is shown together with an example of its operation.

In the case of this embodiment, the frequency rcK of the clock signal GK is variably set so that the delay time τ4 of the delayed signal with respect to the preceding signal is KP = 100 in terms of the number of clocks, and the frequency rcK of the clock signal GK is variably set.
The shift register 33 is configured to receive a 102-bit leading signal, and the second shift register 34 is configured to receive a 6-bit delayed signal.

Now, in FIG. 8+11, the first shift register 33
contains configuration data Al0I for 102 bits of the preceding signal.
Azoz is fetched and also transferred to the second shift register 34.
is the configuration data A++t~^ for 6 bits of the delayed signal,
. 2 is included.

This first. When each of the second shift registers 33 and 34 receives one clock signal CK and shifts by one bit, each of the shift registers 33 and 34 and the coincidence determination section 3
5 shifts to the state shown in FIG. 8(2). That is, the first
The configuration data AlO2 of the preceding signal is stored in the shift register 33 of
~A2゜3 and the configuration data A98~Al0I of the delayed signal are respectively taken into the second shift register 34, and the coincidence determination unit 35 receives the data of the final bit serially output from the first shift register 33. A1゜,
However, all bits of data A911~^, which are output in parallel from the second shift register 34. 3 is given,
A match between these data is determined.

FIG. 8(3) shows a state in which each of the shift registers 33 and 34 under the state of FIG. 8(2) has been further shifted by one bit. For each next serial output data A1.2 of shift register 330, each next parallel output data A99-A of second shift register 34. A match is determined between 4 and 4.

The number of losses for each focus of the second shift register 34 is determined by each counter 37A to 37 constituting the counter group 36.
Each is counted individually by X. In this embodiment, the delay time τ4 is set to correspond to Kp = 100 in terms of the number of clocks, so the frequency of coincidence is theoretically accumulated at the position of = 100, as shown by the orthogonal coordinates in the figure. , a correlation peak of the correlation curve will appear.

FIG. 9 shows an example of actual counting results by the counter group 36. In the same figure, the correlation frequency distribution that appears at positions other than □□ and accumulates at positions corresponding to -component number crab = is generated, and as a result, a correlation frequency distribution that centers on the position of K p * sk and spreads on both sides is generated. It is shown that.

Taking such a distribution means that the first shift register 3
As shown in FIG. 10, as the output of 3, when bit data with the same data content (in the case of the figure, bit data of "■" level) is continuous over multiple bits of the clock signal GK, K=, , as well as the position of = ,
, □-3 as well, the output of the second shift register 34 and the data content match, which can be understood from the fact that the number of negative changes is accumulated.

FIG. 11 shows a specific configuration example of the peak detection section 27 in FIG.
A counter group 36 consisting of 7X counters, a plurality of pairs of digital comparators 38 and 39 connected between adjacent bit counters (for example, 37A and 37B), and a data generation section 40 to which a specific output of one digital comparator 39 is given. Contains.

The digital comparators 3B and 39 are for comparing the respective count values between the counters of adjacent bits, and one digital comparator 38 compares the data of the upper 4 bits in magnitude, and the other digital comparator 38 39 compares the data of the lower 4 bits. In addition, in FIG. 11, each counter 37A to 37X
The count values are indicated by A, B, ..., X, and the upper 4 bits of each count value are A0 to A3+...
...In x0 to x3, each bit data of the lower 4 bits and nodes is A4 to A? +...x4 to X, respectively.

Digital comparator 3 for comparing upper bits, respectively
8 is the counting data for the upper 4 bits (A',
B', . . . ,
give to

and a digital comparator 3 for comparing each lower bit.
9, A'>B', B'>C'.

00.・If w'>x', immediately A>B, B>C9
...,..., determine that W>X, and also A'<B', B
'<C', ..., if w'<x', immediately A<B
, B<C,1,..., W<X, but A'
=B', B'=C',...

When w'=x', the count data for the lower 4 bits are compared in magnitude, and then the magnitude between the count values is determined.

Each digital comparator 39 sends out an output corresponding to the comparison result; in this embodiment, A>B, B>C
, . . . Each output vA41 from which an output signal of logic “1” representing the comparison result of w>x is sent is sent to the data generation unit 40.
The parallel input/serial output shift register 42 is connected to each node of the parallel input/serial output shift register 42. Therefore, this shift register 4
2, data whose content corresponds to the state of the output signal of each output line 41, that is, detection data for detecting a correlation peak, is generated, and in the data array of this detection data,
The position of the correlation peak can be detected by determining the position where rOJ switches to "1".

For example, in the case of the example shown in FIG. 11, the output signal for A>B is rOJ, the output signal for B>C, -10, and w>x is "1", so the count value of the second counter 37B It can be seen that B is the maximum and a correlation peak exists at this position.

In the above embodiment, A>B, B>C, . . .

Each output line 41 to which a signal representing the comparison result of W>X is sent
are connected to each bit of the shift register 42, but the invention is not limited to this, and A<B, B<C.

, , , , each output line through which a signal representing the comparison result of W<X is sent can be connected to each bit of the shift register 42.

The data generation section 40 includes, in addition to the shift register 42 described above, a latch section 43 . Counter 44° Clock generator 45
and a delay circuit 46.

A clock is given to the shift register 42 and the counter 44 by the clock generator 45, the counter 44 counts this clock, and the shift register 42 serially outputs bit data with a slight delay from the timing of this clock. . The launch unit 43 latches the count value of the counter 44 at that time when bit data of "1" is given from the shift register 42.
It can be determined whether the count value of Time τ4 can be calculated.

FIG. 12 shows an example of the configuration of the variable clock generating section 25. As shown in FIG. This variable clock generating section 25 is for generating a clock signal CK by variably setting the clock frequency rcx so that the delay time τ4 is a constant value (for example, 100 clocks) in terms of the number of clocks. In the case, the phase comparator 47, the low-pass filter 48. A PLL loop (Phase) including a voltage controlled oscillator 49 and a counter 50
Locked Loop).

The phase comparator 47 receives a reference signal with a reference frequency f0,
Further, the counter 50 is provided with a frequency division ratio r, and the variable clock generator 25 is provided with a reference frequency f.

The clock frequency feK (=r-f6) is changed by changing the magnification of the frequency division ratio r.

Note that in the above configuration, the counter 50 divides the clock signal CK by a frequency division ratio r and supplies the divided clock signal to the phase comparator 47 . The phase comparator 47 detects that the frequency output by the counter 50 is fc+
The phases of the c/r signal and the reference signal having the reference frequency f0 are compared to generate a voltage according to the phase difference. The low-pass filter 48 smoothes the signal input from the phase comparator 47, and the voltage-controlled oscillator 49 oscillates <=rro> at a frequency fc corresponding to the magnitude of the input voltage to generate a clock signal CK.

FIG. 13 shows a method for determining the frequency division ratio r.

In the figure, ro is an initial frequency division ratio given to the variable clock generation section 25 as initial data, and the variable clock generation section 25 is initially based on this initial frequency division ratio r0, and thereafter uses the updated frequency division ratio. Clock frequency f based on ratio r
CK is determined and a clock signal GK is provided to the signal processing section 51. This signal processing section 51 is the first signal processing section. Each second shift register 33, 34 . The coincidence determination section 35 corresponds to the peak detection section 27, etc., and each shift register 33 and 34 takes in a leading signal and a delayed signal in accordance with the timing of the clock signal CK, and the first shift register 33 outputs in series. The second shift register 34 supplies the final bit data and the plural bit data related to the parallel output to the coincidence determining section 35, respectively.

The coincidence determination unit 35 determines whether the data contents match each other, and the number of occurrences is determined by each counter 37A of the counter group 36 for each bit of the second shift register 34.
~37X counts.

A coincidence frequency distribution is obtained by the counting operations of these counters 37A to 37X, and the magnitudes of the counted values are compared by digital comparators 38 and 39 between counters of adjacent bits, and based on the comparison result, the shift register of the data generation unit 40 is At 42, correlation peak detection data is generated. In the data generating section 40, the detection data and the count value of the counter 44 are applied to a latch section 43, and the latch section 43 generates launch data representing the position of the correlation peak and outputs it to the decoder section 28.

The latch data is decoded by the decoder section 28, and a control amount Δr of the frequency division ratio r is assigned according to its contents. For example, when the correlation peak is located at the position of =99 in FIG. 6, +1 is assigned as the control amount Δr. This control amount Δr is added to the previous frequency division ratio r to be updated to a new frequency division ratio r, and by giving this to the variable clock generation section 25, the clock frequency fCK based on this frequency division ratio r is determined. As a result, the clock signal CK is output.

Returning to FIG. 1, the clock signal CK is applied to the counting section 14. This counting section 14 is for calculating the length and speed of the moving object 18 by counting the clock signal CK, and includes a clock counting counter 52. Reference value selection counter 53. Its configuration includes a comparator 54 and a length conversion counter 55.

The clock counting counter 52 is connected to the variable clock generator 2.
The clock signal CK outputted by 5 is counted.

The reference value setting counter 53 is used to preset the number of clocks corresponding to the unit length Δe of the moving object 18 as the counting reference value n, and this preset value is the correlation peak detected by the peak detector 27. It is decided each time according to the position of. Note that in the peak detection unit 27, the count value N of the clock counting counter 52 is a predetermined value N.

(However, the position of the correlation peak is detected when N<n) is reached.

The comparator 54 outputs a constant length pulse signal when the count value N by the clock counting counter 52 reaches the count reference value n presented to the reference value setting counter 53. When this constant length pulse signal is output, the clock counting counter 52 and the counter group 36 of the peak detecting section 27 are simultaneously reset.

The length conversion counter 55 is for counting the constant length pulse signal, and if the total number of pulses is N, the length Pp moving short distance L of the moving object 18 is calculated by the following formula. be able to.

L=ΔI×N...■ Also, when the length conversion counter 55 counts the number of output pulses per unit time, the object
The velocity V of 8 can be found. In this case, it goes without saying that a timer is provided to set the counting time of the length conversion counter 55.

■=ΔIXN'self...■ FIG. 14 shows a state in which the speed ■ of the moving object 18 changes, with time t plotted on the horizontal axis and velocity V of the object 18 plotted on the vertical axis.

In the figure, to indicates unit time, and the area of the diagonally shaded portion corresponds to the distance (length) Δl that the object 18 moves in unit time t0. Also, (a) shows the counting operation of the clock signal CK by the clock counting counter 52, (b) shows the presetting timing of the reference value setting counter 53, and (c) shows the timing of presetting the reference value setting counter 53.
(d) is the timing of peak detection by the peak detector 27, and (e) is the clock signal G.
The timing of updating the frequency fCK of K is shown respectively.

Next, the operation of the above embodiment will be explained.

When the moving object 18 is irradiated with laser light, the reflected light generates a speckle pattern, and this speckle signal is used as the first. The light is received by each second light receiver 19,20. This light reception signal is given to the signal processing section 12 and binarized, and the binarized output is given to the polarity correlator 13 as a leading signal or a delayed signal.

In the polarity correlator 13, the variable clock generator 25 generates a clock frequency f based on the initial frequency division ratio r0 and the updated frequency division ratio r.
ck is determined and the clock signal CK is applied to the shifter section 26. Each of the shift registers 33 and 34 of the shifter unit 26 takes in the preceding signal and the delayed signal in accordance with the timing of the clock signal GK, and the first shift register 33
provides the final bit data related to the serial output, and the second shift register 34 provides the plural bit data related to the parallel output to the coincidence determining section 35, respectively. Match determination unit 35
Then, a match between the data is determined, and the number of negative results is counted by each counter 37 of the counter group 36 for each bit of the second shift register 34. A coincidence frequency distribution is obtained by the counting operation of these counters 37, and the position of the correlation peak is latched by the latch section 43 of the peak detection section 27.

The latch data is decoded by the decoder section 28, the frequency division ratio r is updated according to the content, and by giving this to the variable clock generation section 25, the clock frequency fcK based on the frequency division ratio r for updating is determined. The clock signal CK is output.

This clock signal CK is applied to the clock counting counter 52 of the counting section 14, and its count value N3 is applied to the comparator 54 (see FIG. 14 (al)).

and the count reference value n recently entered in the reference value setting counter 53, and when the two match, a constant length pulse signal is output to the length conversion counter 55 (Fig. 14 [C
)reference).

Prior to this, when the count value N of the clock counting counter 52 reaches a predetermined value NP, the peak detection unit 27 executes the correlation peak detection operation (see FIG. 14(d)), and the correlation peak The clock frequency fCK is updated based on the detection result (see Figure 14+Q))
, the counting reference value n is determined and preset in the reference value setting counter 53 (see FIG. 14(b)).
.

Therefore, the comparator 54 is connected to the clock counting counter 5.
By comparing the count value N of 2 with this precent value, measurement errors can be minimized, especially when the moving object 18 is accelerating or decelerating.

In this way, the length conversion counter 55 counts the constant length pulse signals, and the total number of pulses (N) determines the length (travel distance) L of the object 18, and the number of output pulses per unit time (N).
', the velocity V of the object 18 can be determined.

<Effects of the Invention> As described above, the present invention provides the first method for receiving scattered light on the surface of an object. The second light receivers are arranged at a predetermined distance apart, and a variable clock generator generates a clock frequency so that the delay time of the light reception signal by the second light receiver with respect to the light reception signal by the first light receiver is a constant value in terms of the number of clocks. is determined and generates a clock signal, and this clock signal is counted by a clock counting section, and a calculation section is performed based on a comparison between the counted value and a counting reference value that is set in the reference value setting section each time a correlation peak is detected. calculates the length and distance of the object, which makes it possible to perform accurate measurement processing in real time, and achieves the purpose of the invention, such as shortening the time required to detect the length and speed of a moving object. be effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the overall schematic configuration of a length/velocity measuring device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the light emitting/receiving system, and FIG. 3 is a block diagram of the signal processing section. A block diagram showing the configuration, FIG. 4 is a time chart of each part of the circuit in FIG. 3, FIG. 5 is a block diagram showing the circuit configuration of the polarity correlator, and FIG. 6 shows the circuit configuration of the polarity correlator and its operation. FIG. 7 is an explanatory diagram showing the operation of the shift register and the match determining section. FIG. 8 is an explanatory diagram showing a specific configuration example of the shift register and the match determining section and an example of its operation. FIG. 9 is an explanatory diagram showing the operation of the shift register and the match determining section. FIG. 10 is an explanatory diagram showing the correlation frequency distribution related to counting. FIG. 10 is a time chart for explaining the reason for generating the correlation frequency distribution in FIG. 9. FIG. Figure 12 is a block diagram showing an example of the circuit configuration of the variable clock generation section, Figure 13 is an explanatory diagram showing how to determine the division ratio in the variable clock generation section, and Figure 14 is an explanatory diagram showing the principle of measuring length and speed. , FIG. 15 is an explanatory diagram of the principle of a speckle speed meter, FIG. 16 is an explanatory diagram showing the configuration of a conventional example, and FIG. 17 is an explanatory diagram showing a correlation curve. 11...Light emitting/receiving system 13...Polar correlator 1
4... Counting section 15... Semiconductor laser 1
9.20... Light receiver 25... Variable clock generation section 27... Peak detection section 52, 53.55... Counter 54... Comparator

Claims (4)

[Claims] (1) A light projector for irradiating light onto a moving object, first and second light receivers arranged at a predetermined distance apart for receiving scattered light on the surface of the object, and a first light receiver a variable clock generating section that determines a clock frequency and generates a clock signal so that the delay time of the light reception signal by the second light receiver with respect to the light reception signal by the second light receiver becomes a constant value in terms of the number of clocks; and a clock for counting the clock signal. a counting section; a peak detection section for detecting a correlation peak at an arbitrary clock signal timing between the light reception signals from the first and second light receivers; a reference value setting section for setting the number of clocks corresponding to a predetermined length as a counting reference value; and a reference value setting section for setting the number of clocks corresponding to a predetermined length as a counting reference value; A length/velocity measuring device comprising a calculation section for calculating the length/velocity of. (2) The length/velocity measuring device according to claim 1, wherein the projector includes a semiconductor laser. (3) The variable clock generating section generates the clock signal by variably setting the clock frequency based on the cross-correlation value of the light signals received by each of the first and second light receivers. Length/speed measuring device. (4) The calculation unit includes a comparator that outputs a constant length pulse signal when the count value of the clock counting unit matches a counting reference value, and a comparator that counts the constant length pulse signal to determine the length and speed of the object. A length/velocity measuring device according to claim 1, further comprising a counter.