JPS63141356A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS63141356A
JPS63141356A JP61288264A JP28826486A JPS63141356A JP S63141356 A JPS63141356 A JP S63141356A JP 61288264 A JP61288264 A JP 61288264A JP 28826486 A JP28826486 A JP 28826486A JP S63141356 A JPS63141356 A JP S63141356A
Authority
JP
Japan
Prior art keywords
semiconductor circuit
surface insulating
insulating layer
metal stud
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61288264A
Other languages
English (en)
Other versions
JPH07112041B2 (ja
Inventor
Akiteru Rai
明照 頼
Keiji Yamamura
山村　圭司
Takashi Nukui
貫井　孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP61288264A priority Critical patent/JPH07112041B2/ja
Priority to DE8787117737T priority patent/DE3781247T2/de
Priority to EP87117737A priority patent/EP0270067B1/en
Priority to US07/128,437 priority patent/US4818728A/en
Publication of JPS63141356A publication Critical patent/JPS63141356A/ja
Publication of JPH07112041B2 publication Critical patent/JPH07112041B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate

Landscapes

  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、複数枚の半導体集積回路基板を積層してなる
半導体装置の製造方法に関する。
〈従来の技術〉 近年、半導体集積回路（以下、ＩＣと略す）の１チップ
当りの集積度は、微細加工技術と設計技術の進歩に伴っ
て急速に向上し、ＩＣの設計基準寸法を変えることなく
さらに高集積化、高性能化を図るべくいわゆる３次元Ｉ
Ｃが出現した。この３次元ＩＣには、第５図に示す単一
シリコン基板ｌＯ上へ気相成長法等によって絶縁層１１
と半導体層１２を交互に繰り返し形成してなるモノリシ
ックタイプと、第６図に示す複数枚の２次元ＩＣチップ
１４，１４．・・・をフリップチップボンディング法等
によって接続用電極１５，１５．・・・を介して厚さ方
向に接合し、電気的に接続してなるハイブリッドタイプ
がある。そして、第６図のハイブリッドタイプＩＣ１６
は第５図のモノリシックタイプＩＣｌ３に比べて製造技
術上の問題や未解決の課題が少ないため、実用化の可能
性がより高いが、接続用電極１５，１５．・・・が互い
に絶縁されていないため、その相互のピッチＰを２００
μｍ程度以下にすることができず、素子レベルの高密度
な電極接続が難しいという問題があった。
そこで、この問題を解決するため、最近、第７図（ａ）
〜（ｅ）に示すようなハイブリッドタイプ３次元ＩＣの
製造方法が提案されるに至った。即ち、この製造方法は
、次のような手順で行なわれる。
（ａ）ＩＣ基板２０の上面に接続用の電極２１゜２１、
・・・を形成し、これらの電極を覆うように上記ＩＣ基
板２０上面全体に保護膜２２を形成する。
（ｂ）　　保護膜２２に各電極２１に達する穴２３を穿
ち、この穴２３に垂直配線２４を押入する。
（ｃ）　　保護膜２２と垂直配線２４を絶縁性樹脂接着
剤２５でコーティングする。
（ｄ）　　絶縁性樹脂接着剤２５をエツチングして垂直
配線２４の上端面を露出させる。
（ｅ）　　上記（ａ）〜（ｄ）の手順で形成した２枚の
ＩＣ基板２６，２６°を、夫々の垂直配線２４．２４’
が対向するように配置して絶縁性樹脂接着剤２５゜２５
°を互いに当接させた後、両者を熱圧着して接合し、電
気的に接続する。
〈発明が解決しようとする問題点〉 ところが、上記従来のハイブリッドタイプ３次元ＩＣの
製造方法によって全ての接続部で確実な電気的接続を得
るには、全ての垂直配線２４．２４′の端面を平坦にし
、反りのない基板２０，２０°を作製し、熱圧着時にＩ
Ｃ基板全体を均一に加圧する必要がある。しかし、この
ようなことは技術面でも装置面でも難かしい点が多い反
面、そうしない限り電極部で接触不良が発生して、製品
の歩留まりや信頼性の低下をもたらすという問題がある
。
さらに、熱圧着時の温度および加圧力が高いため、接続
されるＩＣ基板２０．２０′の半導体素子が破壊される
虞も大きい。
そこで、本発明の目的は、複数枚のＴＣ基板を互いに素
子レベルで高密度で電気的に接続して、容易かつ歩留り
良（信頼性の高いハイブリッドタイプ３次元ＩＣ等を製
造することができる半導体装置の製造方法を提供するこ
とである。
く問題点を解決するための手段〉 上記目的を達成するため、複数枚の半導体回路基板を積
層してなる本発明の半導体装置の製造方法は、一方の半
導体回路基板の表面絶縁層を部分的に除去して露出させ
た接続用電極部に、上記表面絶縁層から突出するように
金属スタッドを形成し、他方の半導体回路基板の表面絶
縁層を部分的に除去して露出させた接続用電極部にろう
材を充填した後、両方の半導体回路基板を、上記接続用
電極部が対向するように配置して表面絶縁層を互いに当
接さ仕るとともに、上記ろう材中に上記金属スタッドが
埋め込まれるように加温することにより、両方の半導体
回路基板を接合し電気的に接続することを特徴とする。
〈実施例〉 以下、本発明を図示の実施例により詳細に説明する。
第１図（ａ）は一方の半導体回路基板の縦断面図を示し
、１は図示しない機能素子を内蔵する半導体回路基板、
２はこの半導体回路基板１の上面に所定間隔をあけて形
成したＡｆｆ等からなる接続用の電極、３は上記半導体
回路基板ｌの上面および電極２を覆って形成したＳｔｏ
ｗ、ＳＩＮ等からなる表面絶縁層、４はこの表面絶縁層
３を部分的に除。
去して露出させた上記電極２に、表面絶縁層３から突出
するように形成したＣｕ、Ａｕ等からなる金　゛属スタ
ッドである。
また、第１図（ｂ）は他方の半導体回路基板の縦断面図
を示し、ｌｏは半導体回路基板、２゛は接続用の電極、
３°は表面絶縁層、５はこの表面絶縁層３゛を部分的に
除去して露出させた上記電極２゜上に、表面絶縁層３゛
から没入するように充填したＳｎ、Ｐｂ４ｎ等からなる
ろう材であり、上記部材１’、２’、３’の構造および
材質は前述の第１図（ａ）のものと同様である。
上記構成の一対の半導体回路基板１．１’は、第１図（
Ｃ）に示すように、夫々の接続用の電極２．２゜が対向
するように位置合わせされ、表面絶縁層３゜３°を互い
に当接せしめられるとともに加温される。そうすると、
電極２°上に盛られたろう材５が溶融し、溶融したろう
材を表面絶縁層３°上に溢れ出させることなくこの溶融
ろう材中に電極２の金属スタッド４が浸漬され、再びろ
う材が固まると、金属スタッド４がろう材５中に埋め込
まれて固定される。これによって、一対の半導体回路基
板１．１°は、互いに接合され、両店板の機能素子か電
極２．金属スタッド４．ろう材５．電極２°を介して電
気的に接続されて、半導体装置が完成される。このよう
に、ろう材５を溶融させる加温温度は従来の熱圧着温度
よりも相当低く、また両方の半導体回路基板ｔ、ｔ’に
は熱圧着時のような高い加圧力が加わらないため、両店
板の機能素子が破壊されることもなく、金属スタッド４
が溶融したろう材５中に埋め込まれるので、従来法のよ
うに基板等に高精度の加工を要さず、また接合条件を厳
格に管理せずとも、接触不良のない確実な電気的接続が
容易に得られる。
第２図は半導体回路基板の変形例を示している。
この変形例では、金属スタッド６を円柱状とし、一方の
半導体基板１を覆う表面絶縁層３に、金属スタッド６が
丁度嵌り込むような電極２に達する穴７を設けている。
また、第３図は半導体回路基板の他の実施例を示してい
る。この実施例では、他方の半導体回路基板ｌ°を覆う
表面絶縁層３′の表面に絶縁性樹脂接着剤８を塗布して
いる。そして、この基板ビを前述と同様に第４図に示す
ように、一方の半導体回路基板ｌに対向させて位置合わ
せし、絶縁性樹脂接着剤８を介して両表面絶縁層３，３
°を互いに当接せしめるとともに加温して、両店板！、
ビを接合し、電気的に接続している。この実施例によれ
ば、上記絶縁性樹脂接着剤８によって金属スタッド４−
ろう材５間のみならず両店板当接面全体で接着がなされ
るため、両店板間の接合が強固になり半導体装置の信頼
性が一層向上する。上記絶縁性樹脂接着剤８は、勿論、
一方の表面絶縁層３だけに、あるいは両方の表面絶縁層
３．３′に塗布してもよい。
上記、実施例、変形例において、電極２と金属スタッド
４．６の間あるいは電極２°とろう材５の間に金属層を
介在させることもできる。
なお、上記実施例、変形例では２枚の基板を接合して半
導体装置を製造する場合について述べたが、本発明は、
基板の両面に夫々金属スタッド。
ろう材を設ければ３枚以上の基板からなる半導体装置に
も適用できる。
〈発明の効果〉 以上の説明で明らかなように、複数枚の半導体回路基板
を積層してなる本発明の半導体装置の製造方法は、一方
の半導体回路基板の表面絶縁層を部分的に除去して露出
させた接続用？１１ｉ極部に、上記表面絶縁層から突出
するように金属スタッドを形成し、他方の半導体回路基
板の表面絶縁層を部分的に除去して露出させた接続用電
極部にろう材を充填した後、両方の半導体回路基板を、
上記接続用電極部が対向するように配置して表面絶縁層
を互いに当接させるとともに、上記ろう材中に上記金属
スタッドが埋め込まれるように加温することにより、両
方の半導体回路基板を接合し電気的に接続するようにし
ているので、ろう接の加温温度が従来の熱圧着温度より
も相当低く、また両方わらないため、両店板の素子が破
壊されることもなく、溶融ろう材中に金属スタッドを埋
め込むため、基板等の加工や接合条件の管理に手間を要
さずに確実な電気的接続が得られ、高密度電気接続でか
つ信頼性の高い半導体装置を容易かつ歩留り良く製造す
ることができ、実装密度の飛躍的向上、配線長短縮によ
る動作速度の向上、異種チップの組合せによる機能性の
向上に大きく貢献する。
【図面の簡単な説明】
第１図は本発明の一実施例を示す断面図、第２図は本発
明の変形例を示す断面図、第３図、第４図は本発明の他
の実施例を示す断面図、第５図。 第６図は夫々従来のモノリシックタイプおよびハイブリ
ッドタイプの半導体集積回路を示す斜視図、第７図は従
来のハイブリッドタイプ半導体集積回路の製造方法を示
す断面図である。 ！、ビ・・・半導体回路基板、２．２°・・・電極、３
．３′・・・表面絶縁層、４．６・・・金属スタッド、
５・・・ろう材、８・・・絶縁性樹脂接着剤。 第１ＷＪ ｔａ２図 １３図 第４ＴＩ！Ｊ

Claims (1)

    【特許請求の範囲】
  1. （１）複数枚の半導体回路基板を積層してなる半導体装
    置の製造方法において、 一方の半導体回路基板の表面絶縁層を部分的に除去して
    露出させた接続用電極部に、上記表面絶縁層から突出す
    るように金属スタッドを形成し、他方の半導体回路基板
    の表面絶縁層を部分的に除去して露出させた接続用電極
    部にろう材を充填した後、両方の半導体回路基板を、上
    記接続用電極部が対向するように配置して表面絶縁層を
    互いに当接させるとともに、上記ろう材中に上記金属ス
    タッドが埋め込まれるように加温することにより、両方
    の半導体回路基板を接合し電気的に接続することを特徴
    とする半導体装置の製造方法。
JP61288264A 1986-12-03 1986-12-03 半導体装置の製造方法 Expired - Fee Related JPH07112041B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP61288264A JPH07112041B2 (ja) 1986-12-03 1986-12-03 半導体装置の製造方法
DE8787117737T DE3781247T2 (de) 1986-12-03 1987-12-01 Verfahren zum herstellen einer halbleiteranordnung mit mindestens zwei halbleiterchips.
EP87117737A EP0270067B1 (en) 1986-12-03 1987-12-01 Method of making a semiconductor device comprising at least two semiconductor chips
US07/128,437 US4818728A (en) 1986-12-03 1987-12-03 Method of making a hybrid semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61288264A JPH07112041B2 (ja) 1986-12-03 1986-12-03 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS63141356A true JPS63141356A (ja) 1988-06-13
JPH07112041B2 JPH07112041B2 (ja) 1995-11-29

Family

ID=17727933

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EP0270067B1 (en) 1992-08-19
DE3781247D1 (de) 1992-09-24

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