JPS6314376B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an image display device.

Conventionally, this type of image display device sends out an image signal consisting of image data and address data from a central control device, receives this image signal at a terminal display device, and stores the image data in a refresh memory based on the address data. A video signal for displaying an image on a cathode ray tube is formed based on image data written to a predetermined memory address and sequentially read out from the refresh memory. However, in such conventional examples, if image data is written to the refresh memory while ignoring the display timing of the video signal, the image data may be written while the beam is scanning the center of the screen. However, writing and reading from the refresh memory were performed at the same time, resulting in the inconvenience that the image displayed on the cathode ray tube was distorted. The present invention has been made to eliminate such inconveniences, and its main purpose is to change the writing timing of image data to the refresh memory during the period when a blank signal of the video signal is obtained (raster (within the retrace period)
An object of the present invention is to provide an image display device that can write image data to a refresh memory without disturbing the image on a cathode ray tube.
Another purpose is to simplify the operation of writing image data into the refresh memory.

Examples will be described below using figures.

FIGS. 1 and 2 show an embodiment of the present invention, and 1 is a central control unit formed using a microcomputer, which controls an image signal V _P consisting of image data D _P and address data D _A. Send to data bus DB. At the same time, a terminal address _AT for calling a specific terminal display device 2 is sent from the central control device 1. On the other hand, when the terminal display device 2 receives the terminal address A _T that matches its own unique address, the paging detection circuit 6 outputs a paging signal V _C , and when this paging signal V _C is obtained, the input/output Circuit 7 and CRT controller 12 are activated. This input/output circuit 7 is a programmable peripheral interface with 8 bits
Three ports are capable of input/output, and writing and reading of the refresh memory 3 are performed through this input/output circuit 7. Reference numeral 5 denotes a driver receiver circuit which receives the image signal V _P and holds address data D _A and image data D _P in address latches and data latches (not shown), respectively. Further, data indicating the operating state of the terminal display device 2 is sent back to the central control device 1 via the driver-receiver circuit 5. in this case,
The data sent on the data bus DB is of negative logic, and since data processing is performed within the terminal display device 2 using positive logic, the logic is inverted. 8 is an address counter consisting of a presettable counter, and the address data D _A input via the input/output circuit 7 is an address set signal.
It is now preset in _AS . 1
2 is a programmable CRT controller,
Display specifications (interlace, number of digits, number of lines, etc.) can be programmed, and address data Da, raster address R, horizontal and vertical synchronization signals H and V, blank signal B, and cursor display signal when reading refresh memory 3 can be programmed. etc. are output. 10 is a multiplexer that switches the address data D _A ″ input to the refresh memory 3; during normal display, it outputs the read address data Da output from the CRT controller 12, and during writing, it outputs the read address data Da output from the CRT controller 12; 3 is a refresh memory consisting of a random access memory ( _{RAM) for storing one screen worth of image data D P displayed} on the cathode ray tube 16. is 80 characters ×
48 lines = 3840 characters (may be simple figures) can be stored, and the image data D _P corresponding to each character is 2-bit display mode data,
It consists of 16 bits (2 bytes) of data consisting of 3 bits color code data and 11 bits character code data. 11 is a driver circuit for writing image data D _P into the refresh memory 3; Reference numeral 17 denotes a latch, which is used to adjust delays and variations in the access time of the refresh memory 3.
The image data D _P read from the refresh memory 3 is stored, and the character code data is sent to the character generator 13, and the display mode data and color code data are sent to the video signal generation circuit 15 via the latch 18. The latch 17 is also used to latch the address of the programmable character generator 13 when its character pattern is changed. Numeral 19 is a multiplexer that switches the raster address R of the address data input to the character generator 13. During normal display, the raster address R output from the CRT controller 12 is switched to the raster address R when changing the character pattern. The output of 17 is sent to character generator 13. The character generator 13 is a ROM that stores bit configuration patterns (characters, figures).
Each pattern consists of 8 x 8 dots as shown in Figure 3, which is stored in 8 bytes, and each pattern has a character code. By inputting the character code data of the image data D _P assigned and read from the refresh memory 3 and the raster address R output from the CRT controller 12, the pattern corresponding to the character data is Dot configuration data is output. Reference numeral 14 denotes a shift register, which constitutes a so-called vertical conversion circuit that converts dot configuration data consisting of parallel data outputted from the character generator 13 into serial data. The dot configuration data is input to the video signal generation circuit 15. The video signal generation circuit 15 generates display mode data for setting the display mode (flashing, reverse display, etc.), color code data for setting the display color, dot configuration data output from the character generator 13, and
A video signal V _O is synthesized and output based on horizontal and vertical synchronizing signals H, V, blank signal B, cursor display signal, etc. output from the CRT controller 12. 16 is a cathode ray tube that displays images using a raster scan method. By the way, the write control circuit 9 forming the write circuit 4 of the refresh memory 3
is R-S flip-flop F and AND gate
It is formed of an AND, an inverter I, and a monostable multivibrator M, and when the write request signal V _R and blank signal B sent from the central controller 1 are input, the image data D _P is transferred to the refresh memory. At the same time, when writing of the image data D _P to the refresh memory _{3 is completed, a write end signal V E is} output for writing to the refresh memory 3.
This write end signal
The address counter 8 is incremented at V _E.

The operation of the embodiment will be explained below. first,
During normal display, the multiplexer 10 outputs read address data Da sent from the CRT controller 12, and refresh memory 3
The image data D _P at the memory address specified by the read address data Da is sequentially read out from there. The character code data of this image data D _P is input to the character generator 13, and dot configuration data of the pattern to be displayed is obtained.
This dot configuration data is input to the video signal generation circuit 15 via the shift register 14, and the display mode data and blank signal B are input at the same time.
A video signal V _O is formed by
The V _O is sent to the cathode ray tube 16 and an image is displayed on the cathode ray tube 16. In this case, the horizontal and vertical synchronizing signals H and V may be output separately from the video signal V _O. In addition, in the case of color display, R, G, B video signals based on color code data
It is designed to output V _O separately.

Next, the case of writing to the refresh memory 3 will be explained. An image signal consisting of address data D _A specifying the memory address of the refresh memory 3 to which the central control unit 1 wants to write, and image data D _P to be written to that memory address.
When V _P is sent out, this image signal V _P is received by the driver receiver circuit 5 of the terminal display device 2, and the address data D _A and the image data D _P are each held in a latch. Address data _DA is set in address counter 8 by address set signal _AS . By the way, after sending out the image data D _P , the central control device 1 sends out a write request signal _VR . When this write request signal V _R is input to the write control circuit 9, the R.S flip-flop F is set, and when a blank signal B consisting of an OR signal of a horizontal blank signal and a vertical blank signal is input, The output of the AND gate AND becomes H level, the monostable multivibrator M operates, and the write signal V _W is output. This write signal _VW switches the multiplexer 10 to the address counter 8 side, activates the driver circuit 11, and writes the image data D _P to a predetermined memory address in the refresh memory 3. At this time, the R-S flip-flop F is reset at the same time, and the write end signal V _E
is output. The address counter 8 is incremented by this write end signal V _E , and the image data D _P when the image signal V _P that does not include the address data D _A is sent from the central control device 1 is replaced with the previously sent image signal V _P The image data D _P is written to the memory address following the memory address of the refresh memory 3 where the image data D P has been written. Therefore, when writing a string of characters that continues horizontally on the cathode ray tube 16 (usually this type of writing is common), the central controller 1 first sends out the image signal V _P containing the address data D _A. If the address data D _A is set in the address counter 8, the image signal V _P sent out subsequently will be the address data D _A.
It is also possible to omit the setting operation of the address data _DA , thereby simplifying the write operation. Of course, if the image data D _P is to be written continuously as described above, it is necessary to confirm the completion of writing and _then perform the next writing.
The signal is then sent back to the central control device 1 via the driver-receiver circuit 5. In this embodiment, since writing is also performed during the period when the horizontal blank signal is obtained (horizontal retrace period), the writing operation can be performed quickly.

The present invention comprises an address counter consisting of a presettable counter to which address data as described above is preset, a data latch which holds image data, and a write request signal sent from a central control unit and a blank signal of a video signal. A write control circuit outputs a write signal for writing image data to the refresh memory when the image data is written to the refresh memory, and outputs a write end signal when writing of the image data to the refresh memory is completed. The data write circuit is configured to increment an address counter with the write end signal, and convert the image data when an image signal containing no address data is sent from the central control unit to the image of the image signal sent last time. Since the data is written to the memory address following the memory address of the refresh memory where the data was written, the image displayed on the cathode ray tube is not distorted when image data is written to the refresh memory, and the image When data is sequentially written to consecutive memory addresses in the refresh memory, there is no need to set address data, which has the advantage of simplifying the write operation.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of the main part of the same, and FIG. 3 is an explanatory diagram of the operation of the same. 1 is a central control unit, 2 is a terminal display device, 3 is a refresh memory, 4 is a write circuit, 8 is an address counter, 9 is a write control circuit, and 16 is a cathode ray tube.

Claims (1)

[Claims] 1 Sends an image signal consisting of image data and address data from the central control unit, receives the image signal at the terminal display device, writes the image data to a predetermined memory address of the refresh memory based on the address data, and performs the refresh operation. In an image display device configured to form a video signal for displaying an image on a cathode ray tube based on image data sequentially read out from a memory, an address counter consisting of a presettable counter to which address data is preset; A data latch holds image data, and outputs a write signal for writing the image data into the refresh memory when a write request signal sent from the central control unit and a blank signal of the video signal are input. A data write circuit of the refresh memory is composed of a write control circuit that outputs a write end signal when writing of image data to the memory is completed, and an address counter is incremented by the write end signal, and the central When an image signal that does not include address data is sent from a control device, the image data is written to a memory address following the memory address of the refresh memory where the image data of the previously sent image signal was written. Characteristic image display device.