JPS6314531A - Reception buffer circuit - Google Patents

Abstract

PURPOSE:To contrive to attain miniaturization and low power consumption of the circuit by applying time series multiplex in the unit of bits to a burst data of plural series and parallel input and storing the result in a storage circuit and applying cyclic check to an output signal of the storage circuit. CONSTITUTION:A parallel input plural series burst data are subjected to time series multiplex in the unit of bits at a parallel/serial conversion circuit 1 and inputted to the storage circuit 2 in a reception buffer circuit of a time division multiple access satellite communication system. The circuit 2 receives a write address from an address generating circuit 3 to store an output of the circuit 1 and receives a read address to convert the multiplex data stored in the unit of bits into a burst data form and outputs the result in time series. As a result, a cyclic check circuit 4 applies required cyclic check as to each burst data inputted sequentially. Thus, even if the parallel input number is increased, since one circuit 4 is enough for the check, the processing is executed simply without increasing the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a reception buffer circuit provided in one station that receives burst data transmitted by N stations using different carrier waves in parallel in a one-to-N communication system. In particular, the present invention relates to a reception buffer circuit having a function of inputting in parallel burst data transmitted by N stations with a cyclic check code added in burst units and determining whether the burst data is correct or incorrect.

(Prior art) For example, in a time division multiple access satellite communication system, when communicating between one station (master station) and many stations (slave stations) via a satellite, there is a limit to the number of lines that can be handled by one carrier wave. Therefore, if there are many lines, multiple carrier waves will be used. That is, the master station receives multiple carrier waves in parallel at once.

In addition, in this type of satellite communication system, the slave station on the transmitting side adds a cyclic check code to the burst data and transmits it, and the master station that receives the burst data at once determines whether the burst data is correct or incorrect. This determination of correctness or incorrectness is performed by a reception buffer circuit.

As such a receiving buffer circuit, for example, the one shown in FIG. 4 is known. This reception buffer circuit has N
cyclic check circuit 4 and parallel-to-serial conversion circuit 1
, a memory circuit 2 , and an address generation circuit 9 .

The N cyclic check circuits 4 are provided in one-to-one correspondence with the carrier waves (assumed to be N series) to be received. The burst data of each carrier wave is input to the parallel-to-serial conversion circuit 1 while undergoing a cyclic check in a corresponding cyclic check circuit 4.

The parallel-to-serial conversion circuit 1 time-series multiplexes N series of burst data inputted in parallel bit by bit, and sends it to the storage circuit 2.

The memory circuit 2 receives address signals of a write address and a read address from the address generation circuit 9, stores the output of the parallel-to-serial conversion circuit 1, and sends it out as output data.

The address generation circuit 9 initializes the write address to the memory circuit 2 in response to a burst start signal generated in synchronization with the input of the N series of burst data, and updates and outputs the write address in response to a write clock signal. Then, the output signal of the parallel-to-serial conversion circuit 1 is sequentially stored in a predetermined storage area of the storage circuit 2.Next, it responds to a read clock signal inputted to read out the burst data stored in the storage circuit 2, which is a reception buffer. Then, the read address is updated and output to the memory circuit 2.

(Problems to be Solved by the Invention) In the conventional receive buffer circuit described above, the number of cyclic check circuits equal to the number of carrier waves is required. As the number of carrier waves increases and the number of carrier waves increases, the circuit scale increases, which poses the problem of hindering miniaturization and power reduction of the device.

The present invention has been developed in view of these conventional problems, and can easily cope with an increase in parallel inputs without increasing the circuit scale, thereby contributing to downsizing and lowering power consumption of devices. The purpose of the present invention is to provide a receiving buffer circuit.

(Means for Solving the Problems) In order to achieve the above object, the reception buffer circuit of the present invention has the following configuration.

That is, the reception buffer circuit of the present invention comprises: a parallel-to-serial conversion circuit that time-series multiplexes burst data consisting of a predetermined number of bits of multiple series input in parallel; a storage circuit; and an output of the parallel-to-serial conversion circuit. an address generation circuit that generates a write address for storing a signal in the memory circuit and a read address for reading out the burst data in time series from the memory circuit; cyclically checking the output signal of the memory circuit; It is characterized by comprising a cyclic check circuit that performs; and;

(Function) Next, the function of the reception buffer circuit of the present invention configured as described above will be explained.

Multiple series of burst data input in parallel are time-series multiplexed bit by bit in a parallel-to-serial conversion circuit and input to a storage circuit. The storage circuit receives the write address from the address generation circuit and stores the output of the parallel-to-serial conversion circuit, and also receives the read address and converts the stored multiplexed data by time-series multiplexing bit by bit into the burst data format. output in chronological order. As a result, the cyclic check circuit can perform the required cyclic check on each burst data input sequentially.

As explained above, according to the reception buffer circuit of the present invention, even if the number of parallel inputs increases, cyclic checks can be performed on all inputs with one cyclic check circuit, so the circuit size does not increase. It can be easily applied without any problems, and has the effect of contributing to the miniaturization of equipment and lower power consumption.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of the configuration of a reception buffer circuit according to an embodiment of the present invention, and FIG. 2 is an operation timing diagram of each part.

This reception buffer circuit basically includes a parallel-to-serial conversion circuit 1, a storage circuit 2, an address generation circuit 3, and a cyclic check circuit 4.

The parallel-to-serial conversion circuit 1 time-series multiplexes burst data consisting of a predetermined number of bits of a plurality of series input in parallel in units of bits based on a high-speed lock signal.

It outputs it to the memory circuit 2.

In this example, in order to simplify the explanation, the number of carrier waves to be input in parallel is assumed to be "2", and the burst data carried by carrier wave 1 has a 4-bit configuration of AO-A3.
)), similarly the burst data carried on carrier wave 2 is BO
~B3 (FIG. 2 (a2)). Therefore, this parallel-to-serial conversion circuit 1 has rAo, BO, Al, B3.
l, A2°B2. A3. Serial data b, B3J, is sent to the storage circuit 2 (FIG. 2(b)).

The address generation circuit 3 is configured, for example, as shown in FIG. 3 (details will be described later), and a burst start signal (second
An address signal ((C)) for storing the serial data b in the memory circuit 2 in response to a high-speed clock signal
In response to a write address) and a read clock signal, each address signal f of a read address for reading out burst data from the memory circuit 2 in time series (FIG. 2(d)) is generated and sent to the memory circuit 2. do.

The cyclic check circuit 4 receives the output signal d (FIG. 2(d)) from the memory circuit 2, and sequentially performs a cyclic check on the input burst data r'Ao-A3J and "Bo~B3J". This is output as output data e (FIG. 2(e)).

Next, a specific example of the address generation circuit 3 will be explained with reference to FIG.

The address generation circuit 3 includes two selection circuits 11 and 12, two counter circuits 13 and 14, and an R-S flip-flop circuit 15.

The first counter circuit 13 is a counter circuit that counts 2 from "0" to "'1" and outputs the upper bit of the address signal f, and performs counting based on the output signal from the first selection circuit 11.

The second counter circuit 14 is 4 from "O" to "3°".
This is a counter circuit that counts and outputs the lower bit 1- of the address signal f, and counts based on the output signal from the second selection circuit 12. When both counter circuits are fully counted, they output a carry signal and also output the count value. It is a flywheel-type empty circuit that returns to "0".

The first selection circuit 11 includes an R-S flip-flop circuit 1
When the output signal of 5 is "1", it outputs a high-speed clock signal with twice the frequency synchronized with the received burst data as it is, and when it is "0°", it outputs the carry signal of the second counter circuit 14. .

The second selection circuit 12 includes an R-S flip-flop circuit 1
When the output signal of 5 is “1°°, the first counter circuit 13
It outputs a carry signal, and when it is "0", it outputs a read clock signal.

The R-S flip-flop circuit 15 sets the output to "1°" when the burst star 1 signal indicating the start position of the received burst data is input, and sets the output to "°" when the carry signal from the second counter circuit 14 is input. O'''.

When the burst start signal shown in FIG. 2(C) is first input to each circuit operating as described above.

The first and second counter circuits 13 and 14 output “0”
That is, the address signal f is initialized, and the output of the R-S flip-flop circuit 15 is set to "1°".As a result, the first selection circuit 11 transfers the high-speed clock signal to the first counter circuit 13. and the second selection circuit 12
outputs the carry signal of the second counter circuit 13 to the second counter circuit 14. The first counter circuit 13 receives the high-speed clock signal and counts from "0°" to "1" while counting the upper bits of the address signal f from "0" to "1".
'' is sequentially outputted. Every time the counting is completed, a carry signal is outputted to the second counter circuit 14 via the second selection circuit 12 and returns to 0.degree.. Each time, the second counter circuit 14 counts up by one, and the lower bit of the address signal f is output.

When the second counter circuit 14 counts four times to -3°, it sets the count value to 0°' and outputs a carry signal.Then, this carry signal causes the R-S flip-flop circuit 15 to output an output of "0°", the first selection circuit 11 stops outputting the high-speed clock signal. That is, the write address signal ends. At this time, the first selection circuit 11 stops outputting the high-speed clock signal. In other words, the write address signal ends.
The second counter circuits 13 and 14 set their count values to 0''
'I have to.

The write address signal formed in this way is
As shown in figure (f), the serial data b has bit AO at address (OO) and bit AO at address (10).
Bit A1 goes to address (01) Bit B1 goes to address (11) Bit A2 goes to address (02) Bit B2 goes to address (12)
bit A3 to address (13), bit B3 to address (13)
will be stored respectively.

In this state, the output of the R-S flip-flop circuit 15 is set to "0", so the first selection port 1I111 selects the output (that is, the carry signal) of the second counter circuit 14, and the second The selection circuit 12 selects the read clock signal. Therefore, when the readout clock signal is input after storing the serial data b to the memory circuit 2, the second counter circuit 14 operates before the first counter circuit 13, and when counting from "On" to "3", the digit Outputs a rising signal and returns to “0”. As a result, the memory circuit 2
As shown in figure (f), (00), (01>, (02)
, (03) are accessed in turn, and AOlA
Each bit of I, A2, and A3 will be sequentially output.

That is, burst data of carrier wave l is output.

Next, when the second counter circuit 14 outputs a carry signal, the first counter circuit 13 counts up by one, so in that state, the second counter circuit 14 counts up four counts from "0" to 3'. As a result, the memory circuit 2 stores (10), (11), (
12) and (13) are accessed in turn, and B
O2B1, B2. Each bit of B3 is output in sequence.

That is, burst data of carrier wave 2 is output.

When the second counter circuit 14 counts up, it becomes “0”.
”, and the carry signal is sent to the first counter circuit 1.
3, the first counter circuit 13 counts up and returns to 0''.

In other words, the read address signal ends.

In this embodiment, the case where the number N of parallel inputs is "2" has been described, but it goes without saying that the same idea can be applied even when N becomes larger.

(Effects of the Invention) As explained above, according to the reception buffer circuit of the present invention, even if the number of parallel inputs increases, one cyclic check circuit can perform cyclic checks on all inputs. This can be easily handled without increasing the circuit scale, and has the effect of contributing to device miniaturization and lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a reception buffer circuit according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of each part, and FIG.
The figure is a block diagram of a specific example of the configuration of an address generation circuit, and FIG. 4 is a block diagram of a conventional reception buffer circuit. 1... Parallel-serial conversion circuit, 2... Memory circuit, 3.9... Address generation circuit, 4...
...Cyclic check circuit, 11.12.
...Selection circuit, 13.14...Counter circuit, 15...R-S flip-flop circuit. Agent: Yoshihiro Yahata, Patent Attorney Figure 1 Cat) #! i'lJr'>+'-'s>y'-y
"A'""CaZ) Power throw g-
Leather 21i-zutote 4 BOFh Bz
B3(b) Serial Tee - Evening AO
BOA no B! A2B2A3β3 Address B1
Relatives 1 Row 3, 4 Thatch (Cape 1)
figure

Claims (1)

[Claims] a parallel-to-serial conversion circuit for time-series multiplexing burst data consisting of a predetermined number of bits of multiple series input in parallel; a storage circuit; and a storage circuit for storing an output signal of the parallel-to-serial conversion circuit in the storage circuit. an address generation circuit that generates a write address and a read address for reading out the burst data from the storage circuit in time series; and a cyclic check circuit that performs a cyclic check on the output signal of the storage circuit. A receiving buffer circuit characterized by: