JPS63147367A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly relates to an impurity layer embedded in a substrate and an impurity layer embedded in a trench used for element isolation. The present invention relates to a bipolar semiconductor device that enables high integration by forming conductive materials in contact and using them as electrodes.

(Prior Art) In semiconductor integrated circuits using bipolar transistors, trench isolation is used to electrically isolate each transistor in order to achieve higher integration and higher speed. When trench isolation is used, the isolation width between transistors is shortened, and the parasitic capacitance between each electrode (emitter, base, collector) of the transistor is reduced, enabling high-speed operation.

Furthermore, a bipolar transistor usually uses a buried impurity layer with low resistance, and in order to make electrical contact with this impurity layer, it is necessary to form a deep impurity layer with low resistance.

(Problems to be Solved by the Invention) FIG. 2 shows a cross-sectional view and a plan view of a conventional bipolar transistor. In the figure, 22 is a buried impurity layer, and 29 is a deep impurity layer electrically connected to 22. In order to bring out the buried layer electrode (collector electrode) on the semiconductor surface, the impurity layer 29 must be formed deep and with low resistance. However, forming a deep impurity layer requires a thermal diffusion process at high temperatures and for a long time, and this thermal process causes the impurity profile in other parts, especially the emitter and base, to be exposed, leading to deterioration of the characteristics of the transistor. There is.

In addition, when forming the impurity layer 29, the impurities spread laterally and come into contact with the p-type layer 30 of the base, causing a problem in which the withstand voltage between the collector bases deteriorates, so it is necessary to provide a sufficient distance between the collector bases. , which is an obstacle to higher integration.

The present invention has been made in view of the above points.

It is an object of the present invention to provide a bipolar transistor that can be highly integrated and run at high speed by taking out an electrode (collector electrode 14) of a buried impurity layer without causing deterioration of transistor characteristics.

[Structure of the Invention] (Means for Solving the Problems) The present invention makes it possible to increase integration and speed by using a conductive material formed inside a trench for isolation between elements as an electrode in contact with a buried impurity layer. ing.

(Function) In the present invention, since an electrode that is in electrical contact with the buried impurity layer can be formed in the element isolation region, the area occupied by one transistor can be highly integrated. Furthermore, since it is easy to lower the resistance of the exposed @pole of the buried layer, the performance of the transistor is also improved.

(Example) Process sectional views (a) to (a) showing an example of the present invention in FIG.
This will be explained with reference to a) and a plan view (f).

On the p-type St substrate 11, for example, sb is diffused using a patterned StO film as a mask in a predetermined region to form n0 layers. Next is the mask 5io21f! After removing a, a P-type or N-type S1 is epitaxially grown to a thickness of, for example, 2 to 31 m, and the above n10 layer is buried to form an n middle layer 12. Next, for example, about 8,000 element isolation regions are formed by, for example, the LOCO5 method [FIG. 1(a)].

Here, the buried n+ layer may be formed over the entire surface.

Next, the trench isolation region is patterned, and the SLO□ film and S
A trench groove 17 is formed by etching i.

Next, for example, thermal oxidation is performed to form an insulating film 15 on the side and bottom surfaces of the trench, and then, for example, polysilicon doped with P (phosphorus) is deposited to fill the trench.Next, the upper part of the trench is buttered and the trench is closed. At least a part of the buried polysilicon is etched using, for example, RIE, and the SiO□ film on the side wall of the trench is etched away using, for example, NH4F [FIG. 1(b)].

Next, a polysilicon film doped with, for example, phosphorus as an impurity is deposited, and the trench portion from which the polysilicon has been etched is buried at 1000° C. in an atmosphere of, for example, N.
, and is electrically connected to the buried n-middle layer 16 by heat treatment for 30 minutes. Next, a resist is applied to the surface and the polysilicon on the surface is etched away using an etching method. [
FIG. 1(C)] Next, for example, B (boron) is diffused into a desired region to form the base layer 18 of the vertical NPN transistor.
is formed, and further diffused with, for example, As, to form an emitter layer 19.
form. [FIG. 1(d)] Next, the electrode 201 from the base diffusion layer and the emitter diffusion layer,
2o, and the upper trench groove 20. Also form an electrode at 0
Usually, AQ-5i is used as the electrode, but other metals may be used. In FIG. 1(0), 201 of the vertical NPN transistor is the emitter electrode, 20. is the base electrode, 20a
becomes the collector electrode.

A plan view is shown in FIG. 1(f). The shaded area is the electrode part. As shown in FIG. 1(f), since the trench portion is used as the collector electrode, the area of the transistor can be significantly reduced. Furthermore, a bipolar transistor can be formed without the need to reduce wiring width or wiring space.

In addition, the collector resistance can be reduced without forming a deep impurity layer that reaches the buried nth layer.

Here, the buried layer is not limited to n10 layers but can also be applied to p middle layers. Further, the material for filling the trench groove is not limited to phosphorus-doped polysilicon, but may also be As-doped polysilicon, B-doped polysilicon, W, or Mo.

Metals such as Ti and AQ and their silicides can also be used.

Furthermore, in the above embodiment, both LOGO5 element isolation and trench element isolation are used;
h) Can be formed using only element isolation.

〔Effect of the invention〕

According to the present invention, the area occupied by one bipolar transistor is significantly reduced compared to the conventional example.

High integration becomes possible. Furthermore, there is no need to form a deep impurity diffusion layer that reaches the buried layer, and the collector resistance can be reduced. Furthermore, as the occupied area is reduced, parasitic capacitance between each electrode is also reduced, allowing high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing an embodiment of the present invention, and FIG. 2 is a structural explanatory diagram showing a conventional example. 11.21...P-type silicon 12.22...n+ buried layer 13...P-type epitaxial layer 14, 25.
...LOCO3 oxide film 15.23...Trench sidewall oxide film 16...N+ embedded layer and trench contact part 17
．． 24...Phosphorus-doped polysilicon 18.30...
P10 impurity layer 19...n10 impurity layer agent Patent attorney Nori Chika Ken Yudo Kikuo Takehana Figure 1 Figure 1

Claims (1)

[Claims] A bottom or sidewall portion of the trench separating the semiconductor elements in a device in which a plurality of semiconductor elements are integrated on a substrate and has trench isolation for electrically isolating each of the semiconductor elements. a conductive material buried in the trench in a part of the substrate; an impurity layer in which a conductive material opposite to that of the substrate is buried in the substrate; and an impurity layer in contact with the impurity layer provided on the surface of the substrate and above the trench What is claimed is: 1. A semiconductor device comprising: an electrode;