JPS631484Y2 - - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a data setting device.

Recently, in radio receivers, the local oscillator circuit 1 is configured with a phase-locked loop (PLL) 2, and the (PLL)
Frequency division ratio N of programmable frequency divider 3 that constitutes 2
A so-called synthesizer receiver has been put into practical use in which a local oscillation frequency p is changed in accordance with data from a control circuit 4, and a local oscillation frequency _p is generated in steps of a reference frequency _r by a voltage controlled oscillator 5 acting as a local oscillator.

In such a synthesizer receiver, a method as shown in FIG. 2 has conventionally been implemented as a method for setting frequency division ratio data in the programmable frequency divider 3. That is, programmable frequency divider 3
Latch circuits 7, 7', which are data setting means for storing frequency division ratio data in the cascade-connected frequency dividers 6, 6', constituting the cascaded frequency dividers 6, 6', . , the latch signals L ₁ to _{L 4} are sequentially stored in the latch circuits 7, 7'..., and the frequency dividers 6, 6'...
This is to set the frequency division ratio. By the way, like this
PLL circuits are integrated into a single-chip IC, but in the system shown in Figure 2, when the number of divider stages increases, it is necessary to increase the number of latch signal terminals accordingly, which in turn causes the IC to This is not desirable as the number of pins increases, leading to increased costs.

Therefore, the present invention was devised in view of this point.
It provides a data setting device that can set data without increasing the number of IC pins even if the number of frequency divider stages increases, and is particularly effective as the number of frequency divider stages increases. It is something to do.

An embodiment of the present invention will be described below with reference to FIG.
Components that are the same as those in FIGS. 1 and 2 are indicated by the same figure numbers.

8 counts the control pulses CP from the control circuit 4,
It is a counting means having a decoder function that generates a decimal output, and also receives a reset signal R from the control circuit 4.
It is configured to be reset by 9,
9'... have one input commonly connected to the latch signal L generated from the control circuit 4, and the other input connected to the decimal output of the counting means 8, respectively.
The output of each AND gate 9, 9'... is connected to a latch circuit 7, 7'..., respectively.

Next, the operation of the present invention having such a configuration will be explained. First, it is assumed that certain numerical data are currently set in the latch circuits 7, 7', . . . and the frequency dividers 6, 6', .
At this time, first, the control circuit 4 generates a reset signal R to reset the counting means 8, and the data input to the first stage latch circuit 7 is generated from the control circuit 4 to the data line D. Time
Since the first stage latch signal _L1 is not generated from the AND gate 9, this data is still in the latch circuit 7.
is not entered. However, after that, the first control pulse generated from the control circuit 4 causes the counting means 8 to
becomes “1”, and the latch signal L from the control circuit 4
When the AND gate 9 detects a match, the latch signal _L1 is generated, and the data D is input to the first stage latch circuit 7. Next, the data for the second stage is output to the data line, the AND gate 9' is opened by counting the second control pulse, and the data is output to the second stage latch circuit 7' by the generation of the latch signal _L2 . is input. Thereafter, in the same manner, the AND gates are sequentially opened when the control pulses are counted, and data is input to the latch circuit. The data input to the latch circuits 7, 7'... is transmitted to the frequency dividers 6, 6'...
The frequency dividing ratio of the frequency dividers 6, 6', . . . is set.
As long as the data in the latch circuits 7, 7', . . . are not changed, the frequency division ratios of the frequency dividers 6, 6', . . . are not changed and the same frequency division cycle continues. In this way, even if the number of latch circuits 7, 7', etc. and frequency dividers 6, 6', etc. increases, by controlling the data setting by the counting means 8, the reset signal input terminal R, the control pulse input terminal CP, and the latch signal input terminal Data can be set using the three L input terminals.

As mentioned above, the data setting device of the present invention controls the data setting to the latch circuits by the output of the counting means that counts control pulses, and even if the number of latch circuits increases, the number of input signal terminals does not increase and the data can be set. Settings can be made, which is extremely useful as it prevents an increase in the number of pins when integrating.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an apparatus equipped with a data setting device, FIG. 2 is a conventional example showing a specific configuration of the main part of FIG. 1, and FIG. 3 is a diagram showing the data setting device of the present invention. 3...Programmable frequency divider, 4...Control circuit, 6, 6', 6"...Frequency divider, 7, 7', 7"...
Latch circuit, 8... Counting means.

Claims (1)

[Scope of utility model registration request] a data signal input terminal to which a data signal is supplied; a data setting means for setting the data signal supplied to the data signal input terminal by generating a latch signal; a latch signal input terminal supplied to the data setting means; and a counting means for generating a switching signal to sequentially switch and output the latch signal supplied to the latch signal input terminal to the data setting means when setting the data signal to the data setting means. , a control pulse input terminal for supplying counting pulses to the counting means, a reset input terminal for resetting the counting contents of the counting means, a latch signal supplied to the latch signal input terminal, and switching sequentially generated by the counting means. A data setting device comprising a coincidence detecting means for detecting coincidence with a signal, and configured to sequentially set data signals supplied to the data signal input terminal in the data setting means by the output of the coincidence detecting means.