JPS63155346A - Ram check system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 1) Working examples (Fig. 2) Effects of the invention [Summary ] The present invention is capable of performing RAM (Rando) performed at startup.
DMA (Direct Hel'I
RAM is read, written, and checked at high speed by using the (ory Access) method.

[Industrial Application Field] The present invention relates to a RAM check method, and in particular, the R
Regarding AM read/write check.

In a data processing device equipped with a RAM, in order to improve the reliability of the system, known data is written in this RAM at the time of system startup, and then read out. A read/write check is performed to check consistency.

C. Prior Art l For this reason, conventionally, a processor stores a specific pattern in RAM, the processor reads it, and compares the written data with the read data to perform a RAM read/write check (hereinafter referred to as R/ (referred to as a W check).

In this case, to further improve reliability, repeat the above operation several times while changing the write pattern to
I was doing R/W checking.

[Problems to be Solved by the Invention] By the way, this RAM R/W check was performed by a software process in which a processor inserts data into an address destination using a program, reads it out, and compares it. There was a problem that the W check time could not be made faster and it took time. In particular, as the capacity of the RAM increases, this check takes time and the system start-up time becomes longer.

An object of the present invention is to provide a high-speed RAMI) R/W check in order to solve these problems.

Means for Solving Problem E] To achieve the above object, in the present invention, as shown in FIG. 1, a direct memory access (hereinafter referred to as DMA) control unit 3 is provided in addition to the processor 1 and the RAM 2; data·
A register 4 and a comparator 5 are provided, and the processor 1 receives data.
Fill in register 4. Next, the DMA control unit 3 is activated and writes the data in the data register 4 into the entire RAM 2. Then D M A 1lilJ 111
The unit 3 reads out the data currently stored in the RAM 2, and the comparator 5 sequentially compares the data held in the data register 4.

[Function 1] All the data input to and output from the RAM 3 are sequentially compared by the comparator 5. If there is a discrepancy, the comparator 5 reports this to the processor 1 so that the state of the RAM 2 can be checked. In this case, unlike the software processing of the processor 1, the operation of the DMA control unit 3 is fast, so the RAM 3 can be checked quickly.

[Example 1 An embodiment of the present invention will be described based on FIG.

In Figure 2, the same symbols as in Figure 1 indicate the same parts,
6 is a data buffer, and 7 is an AND circuit.

The processor 1 is composed of, for example, a microprocessor, and writes data to the data register 4, and writes data to the data register 4.
It outputs the /w signal, the address for performing DMA, and the DMA permission signal BA to the DMA control unit 3.

The DMA control unit 3 performs DMA 1Ii on the RAM 2.
It performs II control, and writes and reads data to and from the RAM 2 via the data buffer 6 written in the data register 4.

Data buffer 6 inputs the data in data register 4 to R.
When entering AM2, the data in data register 4 is held once. When writing to RAM2, it turns on and holds the contents of data register 4, but R
It turns off one after another from AM2, and the data buffer? 6
is prevented from being transmitted to the comparator 5.

The AND circuit 7 is turned on when the RAM 2 is written and sends the output of the comparator 5 to the processor, but turned off when the RAM 2 is written.

Next, the operation shown in FIG. 2 will be explained.

First, the processor 1 sets data in the data register 4 when the system starts up. Then, the processor 1 activates the DMA control unit 3 and asks for the presence or absence of a request.

In response to the presence or absence of a request at the start-up of the system, the DMA control unit 3 outputs a request BR requesting the processor 1 to write to the RAM 2. In response, processor 1 sends a permission signal BA and also outputs a write signal W. This write signal W turns off the AND circuit 7. In response to this permission signal BA, the DMA control section 3 outputs a gate signal 8G, turns the comparator 5 into a non-operating state, turns on the data buffer 6, and sends out the set data from the data register 4. . At this time, DM A ffflJ control section 3 is RAM
Since the address of 2 is sent, this data register 4
The data set in is sequentially written into the RAM 2 via the data buffer 6.

When data writing to the RAM 2 is completed, the processor 1 outputs a read signal R in response to a read request from the DMA control section 3, and instructs the DMA control section 3 to read. At this time, the AND circuit 7 is turned on by the read signal R, and the data buffer 6 is disabled. Also DMA
Since the control unit 3 outputs a gate signal at the time of reading, not only the data register 4 but also the comparator 5 are enabled.

In this state, the D M A ll1lJ m unit 3 outputs the address and sequentially reads data from the RAM 2, and the comparator 5
to communicate. At this time, comparator 5 has data register 4.
Since the data set in the RAM 2 is being transmitted, the data read from the RAM 2 as described above are sequentially compared. If the compared data are different, comparator 5
notifies the processor 1 of the interrupt signal I NT via the AND circuit 7 .

As a result, on the processor 1 side, due to the deletion input during the check on this RAM 2, the RAM
The R/W check error in step 2 is processed.

If no mismatch is detected by comparator 5 and the process ends normally, RAM2
It is assumed that the R/W check has been completed.

Of course, this check can be performed not only once but also multiple times.

In this case, the check may be performed using different data each time.

It is also possible to repeat the above operation while changing the contents of data register 4 by configuring data register 4 with a counter and updating its output data every time a certain number of bytes are written in RAM 2. be.

[Effects of the Invention] According to the present invention, the DMA crime prevention system is implemented and RA is implemented in hardware.
Since it is possible to access M, RAM R/W check can be performed faster than a software check using a conventional processor.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. 1...Processor 2...RA M3...D
MAthlIwJ section 4...Data register 5.
...Comparator 6...Data buffer 7...
・AND circuit

Claims (1)

[Claims] In a data processing device comprising a processor (1), a direct memory access control means (3), and a random access memory (2), a data holding means (4) for storing data. and a comparison means (5), a data holding means (4) and a random access memory (
Compare the data read from 2) with the comparison means (5),
A RAM check method characterized by notifying a processor (1) when there is a difference.