JPH03246741A - synchronous control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a computer system having a shared memory connected to a plurality of CPUs via the same bus, and relates to a synchronous control device that performs exclusive control on the shared memory. It is.

[Conventional technology]

Conventionally, as this type of synchronous control device, for example, Japanese Patent Application Laid-open No. 59
As shown in Japanese Patent Application Laid-Open No. 225469 and Japanese Patent Application Laid-Open No. 60-129867, when performing synchronous control, by having the shared memory itself manage exclusive control of the shared memory, the occupancy rate of the memory bus can be reduced and the CPU load can be reduced. There are ways to reduce this.

In the above-mentioned technique, a processor or arithmetic unit is assigned a number to an address that performs exclusive control on a shared memory, and the address can be accessed only when the number is the same. Exclusive control by the number and address of the processor of other numbers,
The advantage of this is that the arithmetic unit does not lock the bus at addresses other than the specified address.

However, in cases where last-and-set is performed, even the above-mentioned technique cannot be expected to be effective in reducing the CPU load and the memory bus occupancy rate.

Figure 3 is for explaining the last-and-set method, which is known as a means of synchronous control using shared memory. (abbreviated as CPII), (2) is the second central processing unit (hereinafter abbreviated as second CPt1), and (3) is the first and second central processing unit.
CPIJ (1) (2) is a shared memory accessed from (2), (4) is a memory hash, and (5) is a semaphore line for exclusive control.

This last-and-set method uses two or more CPt1
Alternatively, when a program accesses a common area of shared memory, its exclusive use is managed using a flag for a specific area, and the access operation of this common area is as follows! (a) At the same time as reading the flag of the specific area of the first CPII (1), the semaphore line (5) for exclusive control of the memory bus (4) is driven.

(b) 1st CPII (1) is CP from Conoflag
LI (2) Determine whether or not the common area is being used.

(c) When the content of the flag is r□, that is, when use of the common area is permitted, the first CPU (1) writes "1" to the flag indicating that it is using the common area.

(d) When the content of the flag is "1", that is, when the common area is in use, the first CPLI (1) waits for the use of the common area to end.

(e) Release the semaphore line (5) at the same time as either process (c) or (e) is completed.

The semaphore line (5) is driven when multiple CPUs specify a specific address to each other like a flag for a specific area. line (5)
The driving CPU will wait until this is released.

(Problems to be Solved by the Invention) Because of the above-described operation, when either CPU (1) or (2) accesses a flag in a specific area, (I) semaphore A series of operations occur: determining whether the line can be driven (II) driving the semaphore line (III) reading the flag (IV) determining the flag (V) writing the flag (Vl) and releasing the semaphore line.

The problem is that (1) to (Vl) cause an increase in the load on CPt1, and (II) to (Vl) cause an increase in the occupancy rate of memory hash (5) because other CPUs or memory hashes cannot be used. There is.

This invention was made to solve the above-mentioned problems, and it is a last resort that can reduce the CPU's memory space occupancy and also reduce the CPU load.
The purpose of this invention is to provide a synchronous control device based on an AND set method.

[Means for Solving the Problems] A synchronous control device according to the present invention provides a computer system having a shared memory connected to a plurality of CPIIs via the same bus, when synchronization control is performed using the shared memory. The shared memory is equipped with a management means for managing exclusive control of the shared memory itself.

(Function) In this invention, by making the shared memory itself perform exclusive control management, the CPU's memory bus occupation rate can be reduced.
Try to reduce PU load.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) to (4) are the same parts as in FIG. 3, and (6) is a synchronization line indicating exclusive control of the shared memory (3).

FIG. 2 shows a block diagram of the shared memory (3), which includes an address storage circuit (3a) that stores the contents of the address sent from the memory bus (4).
, a memory unit (3b), a memory control circuit (3C), and a data determination circuit (3d) that determines whether data from the memory unit (3a) is “O”, and provides exclusive control of the shared memory as described later. It constitutes a management means for managing.

Next, the operation related to the configurations shown in FIGS. 1 and 2 will be explained.

When the first CPU (1) performs synchronous control, first,
When accessing a flag in a specific area of the shared memory (2) from the first CPLI (1), the address is simultaneously driven to the synchronization line (6) and the memory bus (4).

The shared memory (3) is connected to this synchronization line (6) and the memory hash (4).
) are stored in the memory control circuit (3C) and address storage circuit (3a), respectively. When the memory control circuit (3C) receives the synchronization line (6), it controls the memory section (3b) with the exclusive control address given from the address storage circuit (3a).
Issue an instruction to read data to. The memory section (3b) sends the read data to the data determination circuit (3d). The data determination circuit (3d) uses the bit at a determined position of this data as a flag, determines whether the content is r□, and when it is "0", notifies the memory control circuit (3c) . In response to this notification, the memory control circuit (3c) issues an instruction to write the data "1" prepared in advance into the memory section (3b) at an address for exclusive control given by the address storage circuit (3a). In accordance with this instruction, the memory unit (3b) writes "1" to the bit position determined as the flag of that address.
Write.

On the other hand, if the flag read from the memory section (3b) is not "0", no further processing is performed and this synchronous control is ended.

Here, the content of the original flag of the address to be exclusively controlled is returned to the CPLI as is, and when the content is "0",
This means that the shared memory (3) itself has changed the flag to "1", and when the returned content is "1", the shared memory (3) has changed the flag to "1".
3) It means that the process ended without doing anything.

It should be noted that although the above embodiment has been shown with the first CPII (1), similar processing is performed with other CPII (2).

Further, in the above embodiment, the instruction for exclusive control of the shared memory (3) is given using the synchronization line (6), but the most significant bit of the address line of the memory path (4) may also be used. By doing so, it becomes possible to determine that the shared memory (3) is a space for exclusive control of a certain address or higher.

(Effects of the Invention) As described above, according to the present invention, when performing the test-and-set method as a means of synchronization control, the shared memory itself is configured to perform exclusive control. This eliminates the processes of determining whether or not the drive is possible, 2, reading the flag (data at the address to be exclusively controlled) 3, determining the flag 4, writing to the flag 5, and releasing the semaphore line, reducing the CPU load.
Since the memory bus is not occupied during a series of processing, the occupation rate of the memory bus can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a computer system for explaining a synchronous control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of exclusive control of a shared memory according to an embodiment of the present invention.
FIG. 3 is a computer system configuration diagram illustrating a conventional synchronous control device. (1) is the first CPU, (2) is the second CPU,
(3) is a shared memory, (3a) is an address storage circuit,
(3b) is a memory section, (3C) is a memory control circuit, (3
d) is a data determination circuit, (4) is a memory path, and (6) is a synchronization line. Figure 3 Figure Procedural Amendment (Spontaneous) April 1, 1990, Case Indication Patent Application Hei 2-45261, Name of the Invention Relationship with the Person Who Amended the Synchronous Control Device Case Patent Applicant Address Chiyoda, Tokyo 2-2-3 Marunouchi Ward Representative Moriya Shiki Nakajiro Hill 4th Floor 6 Statement of Contents of Amendment Page 2 Line 11, Page 2 Line 16, Page 3 Line 3 and Page 5 Line 5 Correct each description of "last" in the row to "test". that's all

Claims (1)

[Claims] In a computer system having a shared memory connected to multiple CPUs via the same bus, when synchronization control is performed using the shared memory, the invention is characterized by having a management means for managing exclusive control of the shared memory by the shared memory itself. Synchronous control device.