JPS63155351A - Multi-processor system - Google Patents

Abstract

PURPOSE:To improve the reliability of a multi-processor system by using a decoder and a flip-flop which writes a system program of a CPU having a system program area in a shared memory via another CPU and then outputs a signal to inhibit access given from another CPU to the area where the system program is written. CONSTITUTION:A buffer 2 is turned on when a response signal ACK outputted from a CPU 5 and showing the holding state of a buffer 2 is supplied. Thus a conductive state is secured between a CPU bus 11 and a shared bus 3. A flip-flop 10 is set when a resetting signal RST which resets the CPU 1 and 5 is turned on and outputs an enable signal ENB to a decoder 8. Then the flip-flop 10 is reset when the clear signal CLR received from the CPU 1 is turned on and stops the output of the signal ENB. The decoder 8 outputs a holding signal HOLD when a request signal REQ is inputted and the signal ENB is kept turned off. Then the decoder 8 outputs a selection signal SEL2 in response to the address inputted from a shared bus 3 when the signal ACK is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a system in which a plurality of CPUs access a shared memory and a shared memory, and at least one CPU programs its system program area on the shared memory. and other CP
This invention relates to a multiprocessor in which a system program is written into a system program area by U.

[Conventional technology]

Conventionally, in this type of multiprocessor system,
When a system program is loaded into shared memory,
There was a risk that the system program would be destroyed by access by other CPUs.

[Problem that the invention seeks to solve]

An object of the present invention is to provide a multiprocessor system that protects system programs on a shared memory and improves system reliability.

[Means for solving problems]

The multiprocessor system of the present invention is set by a reset signal that resets the system and outputs an enable signal, and is reset and enabled by a clear signal output by a CPU that writes a system program in the system program area on a shared memory. A flip-flop that stops outputting the signal and is connected to the shared hash,
When the enable signal is output from the flip-flop, a hold request signal is output to the CPU having the system program area, a response signal from the CPU in response to the hold request signal, and an access to the shared memory from the other CPUs. When a request signal requesting a system program area is input, only a selection signal is output to select the chip in the system program area corresponding to the address input from the shared bus to access the system program area, and an enable signal is not output from the flip-flop. If not, when the request signal is input, the hold request signal is output, and when the response signal that responds to this signal is input, the system program corresponding to the address accesses an area other than the input system program area. The decoder outputs only a selection signal for selecting a chip other than the area.

(Function) Therefore, after the system program of the CPU that has the area is loaded into the system program area in the shared memory, any access to the area from other cPUs is prohibited, and the system program may be destroyed. can be prevented.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiprocessor system according to the present invention, and FIG. 2 is a flowchart showing the operation of this embodiment.

The CPU 1 and the CPU 5 are connected to the CPU bus 11 via the high bus 772 and the shared bus 3. The shared memory 9 includes the program memory 6 of the CPU 5, cPUl and the CPU 5.
and a data memory 7 used for communication between the decoder 8 and the selection signal SEL output from the decoder 8
, 5EL2 selects each chip. CPU memory 4 is dedicated memory for the CPUI, so if you want to
I can access CPU memory 4 and shared memory 9,
The CPU 5 can only access the shared memory 9.

The buffer 2 is turned on when it receives a response signal CK output from the CPU 5 indicating that it is in a hold state, thereby establishing conduction between the CPU bus II and the shared bus 3. The flip-flop 10 is set when the reset signal R5T that resets the CPUI and the CPU 5 is turned on and outputs the enable signal ENB to the decoder 8, and is reset when the clear enable signal CLR from the CPUI is turned on and outputs the enable signal ENB. Stop outputting.

The decoder 8 is a circuit that selects the program memory 6 and data memory 7 of the shared memory 9, and is a flip-flop! When the enable signal ENB is input from 0, it outputs a hold request signal l0LD that applies a hold to the CPU5, and
When GK is input to the request signal nEQ requesting access to the shared memory 9 from the UI and the response signal from the CPU 5, the selection signal SEL is output according to the address input from the shared bus 3, and the enable signal ENB is turned off. In this case, when the request signal REQ is input, a hold request signal HOLD is output, and when the response signal C is input, a selection signal SEL is output according to the address input from the shared bus 3.

Next, the operation of this embodiment will be explained with reference to the flowchart of FIG.

When the power is turned on, the system enters the initial state, the reset signal R5T is turned on, and the CPLII and CPU
is in the reset state. The flip-flop 10 is set and the enable signal ENB is turned on, and the decoder 8 outputs a hold request signal +10LI) to the CPU 5 (step 21). When the reset signal R5T returns to OFF, the CPU changes from the reset state to the hold state, and outputs CK to the response signal indicating the hold state (step 2
2).

Next, the CPUI writes the program for the CPU 5 into the program memory 6 (step 23). In the write procedure, first, the CPU 1 turns on the request signal REQ and requests the decoder 8 to access the shared memory 9. At this time, the CPU 5 is already in a hold state, and the bus buffer 2
is turned on by the response signal AC, so the signals (address, data, etc.) on the CPU bus 11 are output to the shared bus 3. Since the enable signal ENB is output, the decoder 8 decodes the address on the shared bus 3, turns on the selection signal SEL of the program memory 6, and writes the data on the shared bus 3 into the program memory 6. When the writing is completed, the CPU 1 turns off the request signal REQ and ends the access.

When writing of all programs is completed, the CPU 1 turns on the clear signal CLR to reset the flip-flop 10, and since the output of the enable signal ENB is stopped due to stiffness, the output of the enable signal ENB is stopped, so the selection signal SEL from the decoder 8 is sent to the program memory 6. Access from CPU 1 is prohibited (step 24). When the enable signal ENB turns off, the decoder 8 turns off the halt request signal HOLD held from the initial state, so the CPU
5 is released from the hold state and enters the run state (step 25), and runs on the program loaded by CPU1 (
Step 26).

Next, the access to the shared memory 9 by cput when the CPU 5 is in the running state will be explained.

When the CPUI turns on the request signal REQ, the decoder 8 turns on the hold request signal HOLD. cp
When us enters the hold state, the CPU 5 turns on the response signal C. When the response signal C is turned on, path buffer 2 is opened and the data on CPU bus II is transferred to shared bus 3.
is output above. When the decoder 8 recognizes the ON state of the response signal ACH, it decodes the address on the shared lotus 3,
Checking which memory in the shared memory 9 the CPU 1 is requesting to access, the request is made to the program memory 6, and since the enable signal ENB is off at this time, the selection signal SEL is turned off. (noma) as C
Access by the PU 1 is prohibited, and if the request is to the data memory 7, the selection signal 5EL2 is turned on to cause the CPU 1 to access the memory. The CPU 1 turns off the request signal REQ and ends the access. Decoder 8
recognizes the off state of the request signal REQ and turns off the halt request signal +10Lfl. This will cause cpus
changes from the hold state to the run state, and the response (3qA(1
: Turn off K.

As described above, when the CPU 5 enters the run state, the flip-flop IO prohibits access from the CPU I to the program memory 6, and the contents of the program memory 6 are protected.

〔Effect of the invention〕

As explained above, in the present invention, after a system program of a CP [J having a system program area in a shared memory is written by another CPU, a signal is output that prohibits access from the other CPU to the area. By providing a flip-flop and a decoder, it is possible to easily protect the system program set on the shared memory, which has the effect of improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the multiprocessor system of the present invention, and FIG. 2 is a flowchart showing the operation of this embodiment. 1... CPU, 2... Buffer, 3...
・Shared bus, 4...-CPU memory, 5...
CPU, 6...Program memory, 7...
・Data memory, 8...Decoder, 9...Shared memory, IO...Flip-flop, 11...
・CPU bus, RST...Reset signal, GLR...Clear signal, ENB...Enable signal, REQ...
Request signal, +10LD...Hold request signal, SEL, 5EL2...Interpretation signal, AGK...
response signal.

Claims (1)

[Claims] A plurality of CPUs have a shared bus and a shared memory, at least one CPU has its system program area on the shared memory, and the other CPUs have a system program in the system program area. In the multiprocessor to be written, a C that is set by a reset signal that resets the system, outputs an enable signal, and writes the system program into the system program area on the shared memory.
A flip-flop that is reset by the clear signal output by the PU and stops outputting the enable signal, and a flip-flop that is connected to a shared bus and sends a hold request signal to the CPU that has the system program area when the enable signal is output from the flip-flop. An address for accessing the system program area input from the shared bus when a response signal from the CPU that responds to the hold request signal and a request signal requesting access to the shared memory from the other CPU are input. outputs only a selection signal for selecting a chip in the system program area corresponding to the flip-flop, and when the enable signal is not output from the flip-flop, outputs the hold request signal when the request signal is input, and responds to this signal. and a decoder that outputs only a selection signal for selecting a chip other than the system program area corresponding to the input address for accessing an area other than the system program area when the response signal is input. processor system.