JPS63166247A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to an electrode or electrode wiring mainly composed of polycrystalline silicon and a method for manufacturing a semiconductor device. The present invention relates to a method of forming an insulating film.

(Prior Art) Many semiconductor devices use a laminated film, in which a polycrystalline silicon film is formed on an insulating film on the main surface of a semiconductor substrate, and an insulating film is further formed on the polycrystalline silicon film, as an electrode or an electrode wiring. An example of such a semiconductor device is an EFROM (ultraviolet erasable rewritable read-only memory), and the manufacturing process of its memory cell will be explained with reference to FIGS. 3(a) and 3(b). That is, first, as shown in FIG. 3A, a first thermal oxide film 33 having a thickness of approximately 100 mL is formed on the surface of an island-shaped element region surrounded by a field oxide film 32 of a P-type silicon substrate 31. , then about 1000X thick on top of it
A first polycrystalline silicon film 34 is formed by low pressure C2 method (chemical vapor deposition method). Next, after doping the polycrystalline silicon film 34 with phosphorus by thermal expansion, about 1000
Thermal oxidation is performed at .degree. C. to form a 20th thermal oxide film 35 having a thickness of 500.times. Next, a second polycrystalline silicon film 36 for control booting is deposited over the entire surface. Next, the second polycrystalline silicon film 36, second thermal oxide film 35, first polycrystalline silicon film 34, and first thermal oxide film 33 are sequentially etched by photolithography (Fig. 3). As shown in the figure, the control route 36', the second dirt oxide film 35'
, a floating root 34' and a first oxide film 33' are formed. Next, using these laminated films as a mask, N-type impurity ions are implanted, and heat treatment is performed.
A type drain region 37 and a type 1 source region 38 are formed, and a +V film 39 is formed on the outer surface of the laminated film. next,
After depositing a passivation film (for example, a PSG film) 40 on the entire surface, selectively etching is performed to open a contact hole, and then an aluminum-silicon film is deposited on the entire surface, followed by t4 turning to form a drain electrode 41 and a source electrode 42. form.

The EPROM cell shown in FIG. 3(b) has an N+ type drain region 37 of a cell transistor and a control gate 36.
By applying a high positive voltage to
Writing is performed by injecting electrons into .

These injected electrons need to be stored in the floating f-t 34' for a long period of time. However, if a high positive voltage is applied to the control gate 36' due to some accidental cause, the floating ? '-)34
The injected electrons accumulated in the second dirt oxide film 35'
The data may be absorbed into the control f-) 36' through the process, and the memory may be erased without the user's knowledge. This is a fatal flaw for lPROM even if it occurs rarely.

This phenomenon is caused by the low breakdown voltage of the second dirt oxide film 35'.

(Problems to be Solved by the Invention) As described above, the present invention aims to solve the problems caused by the low breakdown voltage of the insulating film laminated on the electrode or electrode wiring mainly composed of polycrystalline silicon. The present invention provides a method for manufacturing a semiconductor device that can improve the breakdown voltage and, when applied to the formation of an EPROM cell, can improve the reliability of the cell.

[Structure of the Invention] (Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention includes a step of forming an amorphous silicon film with a phosphorus concentration of 1×10 1 or less on an insulating film on the main surface of a semiconductor substrate. This step is followed by a first lamination step of forming a polycrystalline silicon film with a phosphorus concentration of 1×1O20crIL-3 or more on the amorphous silicon film, and forming an insulating film on the polycrystalline silicon film. A special feature is that the method includes a second lamination step.

(Function) It is estimated that the amorphous silicon film with a phosphorus concentration of 1×10 cR or less has a high concentration of silicon atom adsorption points.
Using this as a base, phosphorus concentration was continuously applied to 21 x 10”cm.
Since a polycrystalline silicon film of -' or more is deposited, the crystal grain size of this polycrystalline silicon film becomes smaller and becomes denser. Furthermore, by simultaneously diffusing phosphorus during the deposition of the polycrystalline silicon film, drag at the grain interface is eliminated and the phosphorus concentration is uniformly diffused. Therefore, when an insulating film is laminated on the polycrystalline silicon film, the number of localized areas where electric field is concentrated, such as crystal irregularities, is significantly reduced at the interface, and the withstand voltage is improved.

(Example) Hereinafter, with reference to the drawings, EPRO will be described as an example of the present invention.
A method for manufacturing a capacitor having a flat plate electrode formed in M will be described in detail. As shown in FIG. 1, an insulating film (approximately 500× thick
A first thermal oxide film) 12 is formed. Next, using a low pressure CVD device, the reaction temperature (also called deposition temperature) was 400°C.
By thermally decomposing 7 run gas (SiH2) at ~600°C and diffusing phosphorus, an amorphous silicon film with a phosphorus concentration of 1 x 10"cm-" or less (for example, lxlQ"m-") is formed. 13 is deposited on the insulating film 12 to a thickness of at least 30X. In this case, if the reaction temperature is below 600°C, insulation #J, ? The amorphous silicon film 13 is formed with almost no progress in crystallization of the silicon atoms adsorbed to the silicon atoms.

Further, it is necessary to cover the surface of the insulating film 12 with an amorphous silicon film 13 having a uniform areal density, and on the other hand, since the deposition rate of the amorphous silicon film 13 is slow, it is necessary to form a film that is thicker than necessary. This would take too much time, so it is desirable to have a thickness of about 30X. Next, the amorphous silicon film 1
Continuing with the formation step 3, that is, without exposing the substrate to the outside air, the reaction temperature is raised to 600° C. to 800° C. by low-pressure CVD method, and the phosphorus concentration is increased while diffusing phosphorus onto the amorphous silicon film 13. 1×1020 儂-3 or more (for example, 5× 1
020L3-”) first polycrystalline silicon film 14 of about 1
000X thickness (this process is repeated in the first
). In this case, at a reaction temperature of 600° C. or higher, silicon atoms adsorbed on the surface of the amorphous silicon film 13 are crystallized to form crystal grains. Furthermore, it is estimated that on the surface of the amorphous silicon film 13, silicon atom adsorption points are uniformly present at a higher density than on the surface of an oxide insulating film formed by a conventional manufacturing method. The silicon adsorbed on the amorphous silicon surface becomes a large number of crystal grains with a small grain size, and a dense first polycrystalline silicon film 14 with few irregularities is formed.

The first polycrystalline silicon film 14 has low resistance because phosphorus is diffused during formation.

Next, the first polycrystalline silicon film 1 is heated to about 1000°C.
4 is thermally oxidized to form a second thermal oxide film 15 having a thickness of 500X (this process will be referred to as a second lamination process). The thermal oxide film 15 becomes a dielectric layer of this capacitor, and the first polycrystalline silicon film 14 becomes one capacitor electrode.

Next, a second polycrystalline silicon film 16 (to be the other capacitor electrode) having a thickness of about 35,001 mm and a sheet resistance of about 200 is deposited on the thermal oxide film 15. Next, the laminated film is etched by photolithography to form the capacitor shown in FIG.

In the manufacturing method described above, the phosphorus concentration I
The phosphorus concentration I X I Q" an-
Since three or more polycrystalline silicon films 14 are deposited, the polycrystalline silicon/film 14 has a small crystal grain size (for example, one
00X or less), resulting in a dense film. Moreover, since phosphorus is diffused at the same time as the polycrystalline silicon film 14 is deposited, the time required for the process is reduced compared to the case where the polycrystalline silicon film is formed and then the phosphorus is diffused as in the conventional manufacturing method. At the same time, traps at grain boundaries are eliminated, and the phosphorus concentration is uniformly diffused. Therefore, when the insulating film 15 is laminated on the polycrystalline silicon film 14, the number of localized areas where electric field is concentrated, such as crystal irregularities, is greatly reduced at the interface, and the withstand voltage is improved.

Here, a capacitor formed by the above manufacturing method,
FIG. 2 shows the results of a comparative measurement of the holding pressure with a gear/fourth gear formed by a conventional manufacturing method. Here, the vertical axis represents the second thermal oxide film 1 when a voltage is applied between the first polycrystalline silicon film 14 and the second polycrystalline silicon film 16.
5, the horizontal axis represents the phosphorus concentration of the first polycrystalline silicon film 14, and the vertical component that intersects with the measured value represents its dispersion. As is clear from this characteristic diagram, the withstand voltage of the capacitor is improved by the above manufacturing method.

In addition, in the above embodiment, in the second lamination step, the first
Although the polycrystalline silicon film 14 is thermally oxidized and the insulation g (silicon oxide film 15) is deposited, the same effect as in the above embodiment can be obtained even if other insulators are deposited.

Although the above embodiments have been described with respect to EPROM capacitors, the present invention is not limited to this, but is applicable to other semiconductors having a component in which an electrode or electrode wiring mainly composed of polycrystalline silicon is opposed to another conductive layer with an insulating film interposed therebetween. equipment (EPR mentioned above)
Of course, the present invention can also be applied to OM cells (OM cells, etc.).

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to improve the withstand voltage of an insulating film laminated on an electrode or electrode wiring whose main component is polycrystalline silicon. For example, when applied to the formation of cells and capacitors in EPROMs, cell reliability and capacitor breakdown voltage can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a method for forming an EPROM capacitor according to an embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 2 is a cross-sectional view of the capacitor shown in FIG. A diagram illustrating the relationship between the phosphorus concentration of the first polycrystalline silicon film serving as one capacitor electrode in the capacitor and the breakdown voltage of the second thermal oxide film serving as the dielectric layer, in comparison with the characteristics of a conventional example; Figure 3 (
&), (b) is a sectional view showing the manufacturing process of a conventional EPROM cell. 1 No... Semiconductor substrate, 12... First thermal oxide film, 1
3... Amorphous silicon film, 14... Polycrystalline silicon film, 15... Second thermal oxide film. Appearance / Standing Representative Patent Attorney Takeshi Suzue Usage 1 Figure 9 〉JA CX To"cm') Figure 2

Claims (2)

[Claims] (1) Phosphorus concentration 1×10^ on the insulating film on the main surface of the semiconductor substrate
A step of forming an amorphous silicon film with a thickness of 2^0 cm^-^3 or less, and a step of forming a polysilicon film with a phosphorus concentration of 1 x 10^2^0 cm^-^3 or more on the amorphous silicon film following this step. A method for manufacturing a semiconductor device, comprising a first lamination step of forming a crystalline silicon film and a second lamination step of forming an insulating film on the polycrystalline silicon film. (2) The thickness of the amorphous silicon film is at least 30 Å.
A method of manufacturing a semiconductor device according to claim 1, characterized in that: