JPH036655B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to an electrode or electrode wiring mainly composed of polycrystalline silicon and a method for manufacturing a semiconductor device. The present invention relates to a method of forming an insulating film.

(Prior Art) Many semiconductor devices use a laminated film, in which a polycrystalline silicon film is formed on an insulating film on the main surface of a semiconductor substrate, and an insulating film is further formed thereon, as an electrode or an electrode wiring. As an example of such a semiconductor device
Taking EPROM (ultraviolet erasable rewritable read-only memory) as an example, the manufacturing process of its memory cell will be explained with reference to FIGS. 3a and 3b. That is, as shown in FIG. 3A, first, a first thermal oxide film 3 with a thickness of about 500 Å is deposited on the surface of an island-shaped element region surrounded by a field oxide film 32 of a P ^- type silicon substrate 31.
Next, a first polycrystalline silicon film 34 having a thickness of about 1000 Å is formed thereon by low pressure CVD (chemical vapor deposition). Next, the polycrystalline silicon film 34 is doped with phosphorus by thermal diffusion, and then thermally oxidized at about 1000°C to a thickness of 500°C.
A second thermal oxide film 35 having a thickness of Å is formed. Next, a second polycrystalline silicon film 36 for a control gate is deposited over the entire surface. Next, a second
polycrystalline silicon film 36, second thermal oxide film 35,
The first polycrystalline silicon film 34 and the first thermal oxide film 33 are sequentially etched to form a control gate 36', a second gate oxide film 35', a floating gate 34' and a first gate oxide film 34', as shown in FIG. A gate oxide film 33' is formed. Next, using these laminated films as a mask, N-type impurity ions are implanted.
Heat treatment is performed to form the N ⁺ type drain region 37 and
An N ⁺ type source region 38 is formed and an oxide film 39 is formed on the outer surface of the laminated film. Next, after a passivation film (for example, a PSG film) 40 is deposited on the entire surface, contact holes are formed by selective etching, and an aluminum-silicon film is further deposited on the entire surface and patterned to form a drain electrode 41 and a source electrode. Electrodes 42 are formed.

The EPROM cell shown in FIG. 3b performs writing by applying a high positive voltage to the N ⁺ type drain region 37 and control gate 36' of the cell transistor and injecting electrons into the floating gate 34'. . These injected electrons need to be stored in the floating gate 34' for a long period of time.
However, when a positive high voltage is applied to the control gate 36' due to some accidental cause, the injected electrons accumulated in the floating gate 34' pass through the second gate oxide film 35' and return to the control gate 36'. ′, and your memory may be erased without you even realizing it. This is a fatal flaw for EPROMs, even if it occurs rarely. This phenomenon is caused by the second
This is due to the low breakdown voltage of the gate oxide film 35'.

(Problems to be Solved by the Invention) As described above, the present invention aims to solve the problems caused by the low breakdown voltage of the insulating film laminated on the electrode or electrode wiring mainly composed of polycrystalline silicon. The present invention provides a method for manufacturing a semiconductor device that can improve the breakdown voltage and, when applied to the formation of an EPROM cell, can improve the reliability of the cell.

[Structure of the Invention] (Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention includes forming an amorphous silicon film with a phosphorus concentration of 1×10 ²⁰ cm ^-3 or less on an insulating film on the main surface of a semiconductor substrate. Continuing with this step, a phosphorus concentration of 1× is formed on the amorphous silicon film.
The first step is to form a polycrystalline silicon film with a thickness of 10 ²⁰ cm ^-3 or more.
and a second lamination step of forming an insulating film on the polycrystalline silicon film.

(Function) It is estimated that the above amorphous silicon film with a phosphorus concentration of 1×10 ²⁰ cm ^{-3 or} less has adsorption points of silicon atoms distributed in a high concentration, and using this as a base, the phosphorus concentration is 1×10 ²⁰ cm -3 or less ^. Since a polycrystalline silicon film of ³ or more is deposited, the crystal grain size of this polycrystalline silicon film becomes smaller and becomes denser. Furthermore, by simultaneously diffusing phosphorus during the deposition of the polycrystalline silicon film, traps at grain boundaries are eliminated and the phosphorus concentration is uniformly diffused. Therefore, when an insulating film is laminated on the polycrystalline silicon film, the number of localized areas where electric field is concentrated, such as crystal irregularities, at the interface is greatly reduced, and the withstand voltage is improved.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
A method for manufacturing a capacitor having a planar electrode formed on an EPROM will be described in detail. As shown in FIG. 1, an insulating film (first thermal oxide film) 12 with a thickness of about 500 Å is formed on the surface (principal surface) of a silicon substrate 11. Next, using a low-pressure CVD device, silane gas (SiH ₄ ) is thermally decomposed at a reaction temperature (also called deposition temperature) of 400°C to 600°C, and the phosphorus concentration is reduced to 1×10 ²⁰ cm ^-3 or less while diffusing phosphorus ( For example, 1×
10 ¹⁹ cm ⁻³ ) is deposited on the insulating film 12 to a thickness of at least 30 Å. In this case, at a reaction temperature of 600° C. or lower, crystallization of the silicon atoms adsorbed to the insulating film 12 hardly progresses, and an amorphous silicon film 13 is formed.
Further, it is necessary to cover the surface of the insulating film 12 with an amorphous silicon film 13 having a uniform areal density, and on the other hand, since the deposition rate of the amorphous silicon film 13 is slow, it is necessary to form a film that is thicker than necessary. Since this would take too much time, it is desirable to have a thickness of about 30 Å. Next, following the step of forming the amorphous silicon film 13, that is, without exposing the substrate to the outside air,
Raise the reaction temperature to 600℃~800℃ for reduced pressure CVD method.
While diffusing phosphorus onto the amorphous silicon film 13, the phosphorus concentration is increased to 1×10 ²⁰ cm ^-3 or more (for example, 5×10 ²⁰
cm ^-3 ) first polycrystalline silicon film 14 of approximately 1000 Å.
(This process will be referred to as the first lamination process). In this case, at a reaction temperature of 600°C or higher, the amorphous silicon film 13
The silicon atoms adsorbed on the surface of the silicon are crystallized to form crystal grains. Furthermore, it is estimated that silicon atom adsorption points are uniformly present on the surface of the amorphous silicon film 13 at a higher density than on the surface of an oxide insulating film formed by a conventional manufacturing method. The silicon adsorbed on the surface of the amorphous silicon film becomes a large number of crystal grains with a small grain size, and a dense first polycrystalline silicon film 14 with few irregularities is formed. This first polycrystalline silicon film 14 has low resistance because phosphorus is diffused during its formation.

Next, the first polycrystalline silicon film 14 is thermally oxidized at about 1000° C. to form a second thermal oxide film 15 with a thickness of 500 Å (this step will be referred to as a second lamination step). The thermal oxide film 15 becomes a dielectric layer of this capacitor, and the first polycrystalline silicon film 14 becomes one capacitor electrode. Next, a second polycrystalline silicon film 16 (to be the other capacitor electrode) having a thickness of about 3500 Å and a sheet resistance of about 20 Ω is deposited on the thermal oxide film 15. Next, the laminated film is etched by photolithography to form the capacitor shown in FIG.

In the manufacturing method described above, an amorphous silicon film 13 with a phosphorus concentration of 1×10 ²⁰ cm ^-3 or less, in which adsorption points of silicon atoms are estimated to be distributed in a high concentration, is produced.
Since the polycrystalline silicon film 14 with a phosphorus concentration of 1×10 ²⁰ cm ^-3 or more is continuously deposited using the polycrystalline silicon film 14 as a base, the crystal grain size of the polycrystalline silicon film 14 becomes small (for example, 100 Å or less) and the film is formed into a fine film. becomes. Moreover, since phosphorus is diffused at the same time as the polycrystalline silicon film 14 is deposited, the time required for the process is shortened compared to the conventional manufacturing method in which phosphorus is diffused after forming a polycrystalline silicon film. At the same time, traps at grain boundaries are eliminated, and the phosphorus concentration is uniformly diffused. Therefore, when the insulating film 15 is laminated on the polycrystalline silicon film 14, the number of localized areas where electric field is concentrated, such as crystal irregularities, is greatly reduced at the interface, and the withstand voltage is improved.

Here, FIG. 2 shows the results of a comparative measurement of the holding pressure of a capacitor formed by the above manufacturing method and a capacitor formed by a conventional manufacturing method. Here, the vertical axis is the first polycrystalline silicon film 1
The value of the withstand voltage of the second thermal oxide film 15 expressed in electric field strength when a voltage is applied between the second polycrystalline silicon film 16 and the second polycrystalline silicon film 16 shown in FIG. It represents the concentration, and the vertical component that intersects the measured value indicates its dispersion. As is clear from this characteristic diagram, the withstand voltage of the capacitor is improved by the above manufacturing method.

In the above embodiment, the first polycrystalline silicon film 14 is thermally oxidized to form an insulating film (silicon oxide film 15) in the second lamination step, but even if other insulators are deposited, the above Effects similar to those of the embodiment can be obtained.

Although the above embodiment describes an EPROM capacitor, the present invention is not limited to this, but is applicable to other semiconductors having a component in which an electrode or electrode wiring mainly composed of polycrystalline silicon is opposed to another conductive layer with an insulating film interposed therebetween. Of course, the present invention can also be applied to devices (such as the aforementioned EPROM cell).

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to improve the withstand voltage of an insulating film laminated on an electrode or electrode wiring whose main component is polycrystalline silicon. For example, when applied to the formation of cells and capacitors in EPROM, cell reliability and capacitor breakdown voltage can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a method for forming an EPROM capacitor according to an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 1
Figure 3a and b are diagrams showing the relationship between the phosphorus concentration of the polycrystalline silicon film and the breakdown voltage of the second thermal oxide film serving as the dielectric layer, in comparison with the characteristics of a conventional example. FIG. 3 is a cross-sectional view showing the manufacturing process of the cell. 11... Semiconductor substrate, 12... First thermal oxide film, 13... Amorphous silicon film, 14... Polycrystalline silicon film, 15... Second thermal oxide film.

Claims (1)

[Claims] 1. A phosphorus concentration of 1× on the insulating film on the main surface of the semiconductor substrate.
A step of forming an amorphous silicon film with a concentration of 10 ²⁰ cm ^-3 or less, and subsequently forming a polycrystalline silicon film with a phosphorus concentration of 1×10 ²⁰ cm ^{-3 or} more on the amorphous silicon film. A method of manufacturing a semiconductor device, comprising a first lamination step and a second lamination step of forming an insulating film on the polycrystalline silicon film. 2 The thickness of the amorphous silicon film is at least 30
3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness is Å.