JPS6316948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit used for video signal processing and the like.

FIG. 1 is a circuit diagram showing a conventional clamp circuit. In the figure, 1 is a signal input terminal to which an input signal is input, 2 is a capacitor whose one end is connected to this signal input terminal 1, 3 is a pulse input terminal to which a clamp pulse is input, and 4 is one end connected to this pulse input terminal 3. A resistor to be connected, 5 is a first transistor whose base is connected to the other end of this resistor 4 and a collector is connected to the other end of the capacitor 2, 6 is a positive electrode terminal connected to the emitter of the first transistor 5, and a negative electrode terminal. is a variable voltage source connected to ground, and 7 is an output terminal connected to the collector of the first transistor 5.

Next, the operation of the clamp circuit according to the above configuration will be explained.

First, the capacitor 2 is charged by an input signal input to the signal input terminal 1. Then, as the terminal voltage of this capacitor 2 increases, this voltage is applied to the collector of the first transistor 5.
On the other hand, the clamp pulse input to the pulse input terminal 3 is applied to the base of the first transistor 5 via the resistor 4. Therefore, the first transistor 5 is turned on, so that the output terminal 7 becomes a voltage clamped to the voltage of the variable voltage source 6.

However, in the conventional clamp circuit, the input impedance cannot be increased because the clamp pulse input to the pulse input terminal 3 requires a sufficient base current to flow in order to cause the first transistor 5 to perform a sufficient switching operation. Furthermore, since the drive impedance seen from the base of the first transistor 5 is at least the resistance 4, when the first transistor 5 is turned off, it is affected by the accumulated charge and the clamp time cannot be reduced. Further, there was a drawback that the drive current fluctuated due to changes in the amplitude of the clamp pulse or changes in the voltage of the variable voltage source 6.

Therefore, the first object of the present invention is to provide a clamp circuit that lowers the base drive impedance when the first transistor is turned off so that it is not affected by the accumulated charge, and reduces the clamp time. This is what we provide.

A second object of the present invention is to provide a clamp circuit suitable as an IC circuit.

To achieve this purpose, the present invention provides a transistor complementary to the first transistor, the base of which is connected to a pulse input terminal into which a clamp pulse is input, the collector connected to ground, and the emitter connected to the base of the first transistor. a second transistor of
The device includes a constant current source connected between the base of the transistor and ground, and will be described in detail below using examples.

FIG. 2 is a circuit diagram showing an embodiment of the clamp circuit according to the present invention. In the figure, 8 is a second transistor whose base is connected to the pulse input terminal 3, its collector is connected to ground, and its emitter is connected to the base of the first transistor 5, and 9 is a connection between the emitter of the second transistor 8 and ground. A constant current source connected between the

Next, the operation of the clamp circuit according to the above configuration will be explained. First, the capacitor 2 is charged by an input signal input to the signal input terminal 1. Then, as the terminal voltage of this capacitor 2 increases, this voltage is applied to the collector of the first transistor 5. On the other hand, since the clamp pulse input to the pulse input terminal 3 is applied to the base of the second transistor 8, the switching operation of the first transistor 5 is performed by the potential of this clamp pulse. That is, when the emitter-base voltage of the second transistor 8 is about -0.6V, the current of the constant current source 9 flows to the second transistor 8, and the
Transistor 5 is then turned off. Also, the second
The emitter-base voltage of transistor 8 is -
When the voltage is higher than 0.6V, the second transistor 8 is turned off, and the current of the constant current source 9 is lower than that of the first transistor.
It flows into the base of transistor 5 and becomes conductive. Therefore, the capacitor 2 is charged and discharged by the switching operation of the first transistor 5, and the input signal input to the signal input terminal 1 is clamped to the potential of the variable voltage source 6 and output to the output terminal 7.

In this way, since the drive current of the first transistor 5 is supplied from the constant current source 9, it is always constant. Further, the input impedance of the signal input terminal 1 becomes high because the second transistor 8 operates as an emitter follower. Further, when the first transistor 5 is turned off, the second transistor 8 becomes active and the base drive impedance of the first transistor 5 becomes low, so that the accumulated charge in the first transistor 5 can be easily extracted. Since the first transistor 5 burns out quickly, it is not affected by the accumulated charge.

Note that in the above, the emitter of the first transistor 5 is connected to the constant current source 9 and the collector is connected to one end of the capacitor 2, but the collector is connected to the constant current source 9 and the emitter is connected to one end of the capacitor 2. Of course it's a good thing.

Moreover, in the above, the first transistor is NPN type,
Although the second transistor was explained as a PNP type,
Of course, the first transistor may be of PNP type and the second transistor may be of NPN type.

As described above in detail, according to the clamp circuit according to the present invention, the input impedance of the pulse input terminal becomes high, so that the power consumption of the clamp pulse generation circuit can be reduced, which is advantageous for parallel driving. Furthermore, since the influence of accumulated charges is small, there are effects such as a reduction in clamp time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional clamp circuit, and FIG. 2 is a circuit diagram showing an embodiment of the clamp circuit according to the present invention. 1... Input terminal, 2... Capacitor, 3... Pulse input terminal, 4... Resistor, 5... First transistor, 6... Variable power supply, 7... Output terminal, 8...
Second transistor, 9...constant current source.

Claims (1)

[Claims] 1 Charge a capacitor with an input signal, apply the charged voltage to the first transistor, and at the same time, the first transistor becomes conductive due to the input of the clamp pulse, and the potential of the voltage source connected to its emitter or collector is changed to this conductive state. In a clamp circuit that clamps the potential of the output terminal to the potential of the voltage source by applying voltage to the other end of the capacitor through the first transistor of the state, the base is connected to the pulse input terminal where the clamp pulse is input, and the collector is connected to the ground. a second transistor complementary to the first transistor, the emitter of which is connected to the base of the first transistor;
When a constant current source is provided at the connection point with the emitter of the transistor and the first transistor is turned off,
A clamp circuit characterized in that the second transistor is made conductive, the accumulated charge in the first transistor is extracted, and the first transistor is instantaneously turned off.