JPS63181590A - Image signal delay method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention separately digitally encodes a luminance signal and a color signal in a color television image signal.

This relates to an image signal delay method that delays this signal in a memory for a predetermined period of time.

[Summary of the invention]

In a component encoding method that digitally encodes a luminance signal and a chrominance signal (RY signal, B-Y signal) separately, in order to delay each of the above signals by a predetermined time, two types of chrominance signals are used, one for the luminance signal and the other for the chrominance signal. Three sets of memories are required. Especially during the first frame period.

When delaying by one field period, three sets of memories require approximately 120 ICs, resulting in a large circuit scale. Therefore, in the present invention, for the color signal whose sampling frequency is lower than that of the luminance signal, first input the R-Y signal and the B-Y signal to a two-man switch, and switch this switch at twice the sampling frequency of the color signal. After switching alternately at a cycle of 1 to 1, it is input to one set of memories, delayed for a predetermined time, and then output again to R-
Y.

Separate into B-Y signals. As a result, the number of memories that are delayed for a predetermined period is reduced from three to two, and the circuit scale can be configured to the same level as in the conventional diagram. As a result, the circuit can be made smaller, more reliable, lower in cost, and lower in power consumption.

[Conventional technology]

One of the methods for digitizing image signals and performing signal processing is a component coding method in which luminance signals and color signals are individually coded. This method includes high-definition, standard-definition for studio use, and ENG (Electric Ne...
Three families of slightly lower image quality are being considered for use in applications such as WS Gathering. The difference lies in the ratio of the sampling frequencies of the luminance signal and color signal (RY signal, BY signal).

For high image quality, the ratio is 4:4:4. 4 for standard definition
:2:2. For low-level image quality, the ratio is 2:1:1.

When image processing such as still images and noise reduction is performed using such digitally encoded component signals, a memory that delays the time of one field period or one frame period is used to convert luminance signals and two-color signals (R -Y signal,
A total of three sets are required, one set for each (B-Y signal).

An example of configuring a field memory will be explained below. Here, if the sampling frequency of the luminance signal is twice the sampling frequency of the color signal.

The memory control method shown in FIG. 2 is common.

The luminance signal applied to input terminal 1.2.3 and R-Y
The signal and the B-Y signal are stored in field memories 4 and 15, respectively.
．． 16. Then, the luminance signal memory controller 112 and the color signal memory controller 17 are controlled by the luminance signal sampling clock YcK and the two-color multiplication sampling clock CCK to supply addresses and control signals to each field memory, and the luminance signal is delayed by one field. signal, R
-Y signal, B -Y signal respectively output terminal 12.1
Obtained on 3.14.

Next, an example of the circuit configuration of a field memory is shown in FIG. FIG. 3 shows the circuit configuration for one bit when an image signal is digitally encoded. The input 1-bit image signal is transferred to a 4-pit shift register 18.
The data rate is reduced to % of the sampling frequency in the data register 19, and the bit dynamic R is set to 256 with a 4-bit configuration.
AM (Dynamic ndCXnAccess Memory)
The memory controller 11 controls the address and read/write control signals input to the memory 20, and the signals output from the memory 20 are again quickly converted into 1-bit image signals by the data register 21 and 4-bit shift register 22. Delays the field image signal. As described above, since the sampling frequency of the image signal is high, parallel processing is performed to reduce the sampling frequency to a speed that can be processed by the memory.

From the above, the circuit scale in field memory is 1 bit, I
Five Cs are required. Generally, the number of quantization bits of an image signal is 8 bits, so in the case of a component signal, U
Approximately 120 ICs are required to delay the image signal by one field, which is a bit (8 bits x 3 systems) image signal.

Next, regarding the circuit scale of the frame memory, since the storage capacity of the frame memory is twice that of the field memory, it is sufficient to select a dynamic RAM whose capacity is twice that of the field memory. Therefore, it can be considered that field memory and frame memory have approximately the same circuit scale. As described above, in the conventional memory control method, the circuit scale becomes large in order to delay the field period and frame period signals, and it cannot be said to be sufficient in terms of reliability and cost.

[The point that the invention attempts to solve]

It is an object of the present invention to provide an image signal delay method that reduces the current circuit scale.

[Means for solving problems]

In order to achieve the above object, the present invention inputs the R-Y signal and B-Y signal, which are chrominance signals whose sampling frequency is higher than that of the luminance signal, into a two-man powered switch, and uses this switch to sample the chrominance signal. After being alternately switched at a cycle twice the frequency to form one system of color signals, the signals are input to one set of memories, delayed for a predetermined time, and separated into R-Y signals and B-Y signals again. By this operation, the amount of data to be stored and the processing speed are the same for the luminance signal and the color signal, making it possible to use a memory controller in combination.

[Effect]

As a result, the conventional system required three sets of memory for delaying a predetermined time, one for the luminance signal and one for two types of chrominance signals, but now there are two sets, one for the luminance signal and one for the chrominance signal, and an additional memory controller In this case, the luminance signal and the color signal were separated, but the luminance signal can be used in combination, so the scale of nine circuits can be reduced to about 2/3 of the conventional one.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, the memory is field memory.

8-bit RY signal applied to input terminals 2 and 3, B
The -Y signal is input to a switch 5 with two inputs and one output, and is switched at a cycle twice the sampling frequency of the color signal, that is, the color signal sampling clock CCK, to produce one system of color signals. Next, the input is input to the field memory 4, and the memory controller 11 is controlled by the luminance signal sampling clock YCK to delay it by one field period, and then one system of color signals is divided into two systems, one of which only requires one clock YCK. The signal is delayed by the shift register 8, and both systems are latched by the shift register 9 and 10 at the timing of the clock CCK, so that the RY signal and the Fl-Y signal are obtained at the output terminals 13 and 14. On the other hand, 8 added to input terminal 1
The bit luminance signal is input to the field memory 4, controlled by the memory controller 11, delayed for one field period, and then passed through the latch with the nine color signals. In order to correct the time difference caused by this, the shift register 6.7 is input. The signal is output to the output terminal 8 via the output terminal 8.

Next, the operation of FIG. 1 will be explained using the waveform diagram of FIG. 4.

(Q represents the form of each sampling of the luminance signal and color signal RY signal and BY signal at the input terminal 1.2.3.The sampling frequency of the color signal is the same as that of the luminance signal. Since this is the station, one time slot of the chrominance signal is twice that of the luminance signal as shown in the figure. [F] is the sampling clock CC of the chrominance signal.
Represents K. (E represents the state in which the R-Y signal and the B-Y signal are switched by the color signal sampling clock CCK using the switch 5, resulting in one system of color signals. This process allows one time slot of the color signal and the luminance signal. Then, the amount of data of the luminance signal and the color signal combined into one system are equal, and the memory controller -11 for the luminance signal can control the field memory 4 for the color signal. (0 represents the output delayed by the color signal obtained from the field memory in the shift register 8.
Represents a state in which CK is delayed. 0(I) represents a state in which the waveform of (Gl, fF) is latched by the shift register 9.10 at the timing of the color signal sampling clock CCK and restored to the original data rate of the color signal. (Comparing the waveforms of 0, 0, (B), and (I), it can be seen that due to the above processing, the color signal is further delayed by l clocks of the color signal sampling clock during one field period. Therefore, the luminance The signal is delayed by a 2YcK clock shift register 6.7 to adjust the time of the luminance signal and color signal.

〔Effect of the invention〕

According to the present invention, only two sets of memories are required to delay the predetermined time, and a memory controller can also be used in combination, so that it is possible to reduce the size, reliability, cost, and power consumption of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional circuit configuration, and FIG. 3 is a block diagram showing an example of a conventional field memory circuit configuration. FIG. 4 is a waveform diagram showing the operating principle of a circuit according to an embodiment of the present invention.

Claims (1)

[Claims] 1. Component encoding image signals that are individually digitally encoded with the sampling frequency of the luminance signal being twice the sampling frequency of the two types of color signals are stored in a memory in a predetermined manner. In the time-delayed image signal delay method, the above 2
Different types of color signals are input to a 2-input 1-output switch, and the switch is alternately switched at a cycle twice the sampling frequency of the color signal to form one system of color signals. After delaying with memory, controlling and delaying with
An image signal delay method characterized by restoring to two types of color signals. 2. The image signal delay method according to claim 1, wherein the memory control circuit is used in conjunction with another memory control circuit that controls the luminance signal to be delayed in the memory for a predetermined time. .