JPS6318677A - Iii-v compound semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a short channel effect and to implement the high gm of an enhancement type group III-V semiconductor with good controllability, by forming a fluorine-ion implanted region having the depth of implantation distribution, which is thicker than the n-type operating region of the III-V compound semiconductor. CONSTITUTION:An n-type operating layer 11 and an n<+> contact layer 9 are formed in semi-insulating GaAs substrate 1. A fluorine-ion implanted region 12, which has the distribution of implantation deeper than the thickness of the layer 11, is formed so that the region 12 is overlapped with the region of the layer 11. The depth of Si ions (a) and that of the F ions (b) have different values. The F ions are implanted at the same time as the Si ions, which are implanted in the substrate, together. Thus the activating rate and the mobility of the Si ions are made larger than those of the Si ions when only the Si ions alone are implanted. A gate electrode 7 and an ohmic electrode 10 are formed. In this method, a short channel effect is decreased, and a high gm is implemented with good controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a III-V group semiconductor device using an ion implantation method.

(Prior art and its problems) In recent years, with the aim of increasing the speed of semiconductor integrated circuits, G
Development of aAs integrated circuits is actively underway. GaA
Field-effect transistors are generally used as the basic elements of integrated circuits, but ion implantation is widely used as a method for forming the active layer of such elements from the viewpoints of uniformity, controllability, and mass production. .

In order to increase the speed of a GaAs integrated circuit, it is essential to increase the mutual conductance (gm) of a field effect transistor, which is a basic element. In order to obtain a high gm, the gate length of the field effect transistor may be shortened, but if the gate length is made shorter than lpm, the threshold voltage of the field effect transistor changes to the negative side due to the influence of the short channel effect. The short channel effect not only deteriorates the controllability and uniformity of the threshold voltage of a field effect transistor, but also makes it difficult to realize an enhancement type field effect transistor with a high gm.

It has been pointed out that the cause of the short channel effect is the influence of the substrate current flowing between the source and drain n+ contact layers as a space charge limited current.
It has been reported that the reduction can be achieved by providing a p-wall buried layer under the active layer (for example, Yamazaki (K, Yama
saki) and others, Electronics Shiters (Elec
Lett, Volume 20, Page 1029, 1984). Figure 5 shows the concentration distribution of Si and Be atoms when a p-type buried layer is formed using Be ions as the main layer under an n-type active layer formed using Si ion implantation. be. In this method, a considerable amount of Be is also introduced into the n-type active layer into which Si ions are implanted. Be in the n-type active layer causes a decrease in electron concentration and electron mobility in the active layer, and therefore, S
Field effect transistors manufactured by the co-implantation method of i ions and Be ions have the disadvantage that high gm cannot be achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide an NR-V semiconductor device that can reduce short channel effects and achieve high gm.

(Means for Solving the Problems) According to the present invention, in the n-type operating region of a III-V group semiconductor device, a fluorine ion implantation region having an implantation distribution depth equal to or greater than the thickness of the n-type operating region is provided. A Tll-V group semiconductor device is obtained.

(Function) The present invention provides a semi-insulating GaAs substrate with an ion
If the activation rate and mobility of the type impurity are improved by ion-implanting fluorine (F) together with the n-type impurity, and the implantation distribution depth of the fluorine ions is larger than the thickness of the n-type active layer, the electric field This is based on the experimental fact that the dependence of the threshold voltage of an effect transistor on the gate length can be reduced.

(Example) FIG. 1 is a cross-sectional structural diagram of a semiconductor device according to the present invention. An n-type active layer 11 and an n+
A contact layer 9 is formed, and a fluorine ion implantation region 12 having an implantation distribution deeper than the thickness of the n-type operation layer 11 is formed overlapping the n-type operation layer region. Second
The figure shows the depth distribution of each impurity in the n-type active layer 11 and the fluorine ion implanted region 12. As an example, a case is shown in which Si ion implantation is used as the method for forming the n-type operating layer 11. The activation rate and mobility of Si ions implanted into the semi-insulating GaAs substrate 1 are
By co-implanting F ions at the same time as ions, Si
It can be made larger than in the case of single ion implantation. - As an example, 283i ion at 50 keV
A 10'cm-2 semi-insulating GaAs substrate was implanted at room temperature, and further 19F ions were implanted at 40 keV at 2 x 1013 cm.
-2 Similarly, the activation rate and mobility when annealing for 800°Cl2O after room temperature implantation were 45
%.

It was 3000cm2A'-5ec. These values are F
Activation rate and mobility of Si ions without ion implantation (35%, 2800 cm2/V-se, respectively)
This shows a better value than c).

FIGS. 3(a) to 3(g) show cross-sectional structural views of a semiconductor device in the order of manufacturing steps in the case of manufacturing a III-V group semiconductor device according to the present invention. First, a photoresist 2 is used on a semi-insulating GaAs substrate 1 to selectively open a window in only the device formation region, and then Si ions 3 are injected at 10 keV to I x 1013 cm-2, and F ions 4 are injected at 10 keV to 2 x 1013 cm-2, respectively, to form an n-type operating layer 5 (FIG. 3(a),
(b)). After the ion implantation, the photoresist 2 is removed and a 50 nm thick CVDSi3N4 film is deposited as an annealing protective film 6. The active layer 5 is annealed using an electric furnace in a hydrogen atmosphere at 800 DEG C.Cl2O for minutes (FIG. 3(C)).

After that, the annealing protective film was removed and W was used as the gate metal.
Six is sputter-deposited to a thickness of 500 nm. By dry etching with SF6 gas, 0.5.1.0, 1.5,
After forming the gate electrode 7 with each gate length of 2.0 pm (FIG. 3(d)), Si ions 8 were injected at 1×10 at 100 keV as an n-layer for the source and drain regions.
13cm-2 implantation to form n+ contact layer 9 (
Figure 3(e)). Annealing of n middle layer is 800°C110
The annealing is performed using the Si3N4 protective film 6 for the same minutes (FIG. 3(f)).

Next, AuGe-Ni is vacuum-deposited as the source and drain ohmic electrodes 10, and after an alloying process at 420°C, Ti-Au is deposited as a pad electrode on the AuGe-Ni layer.
A field effect transistor is completed by vapor deposition on e-Ni (FIG. 3(g)).

The threshold voltage of the field effect transistor obtained by the present invention is -0.05 V for a device with a gate length of 0.5 pm, the average value of gm is 480 m5/mm, and the maximum value is high, exceeding 60 m5/mm. value was obtained. In a similar device fabricated without F ion implantation, the average gm was 380 m5/mm at threshold voltage -〇, 20V, and F
It has been demonstrated that the average gm can be improved by 20-30% by performing ion implantation.

Further, in the field effect transistor using the present invention, the short channel effect is also significantly reduced. FIG. 4 shows the dependence of threshold voltage on gate length. In the field effect transistor according to the present invention manufactured by co-implantation of Si ions and F ions, the change in threshold voltage due to shortening of the gate length is suppressed to 0.1 V or less.
In the device in which F ion implantation was not performed, the threshold voltage changed by as much as 0.3 μ, demonstrating that the present invention is useful also from the viewpoint of reducing the short channel effect.

In this example, as a method of introducing Si ions and F ions, each independent ion? Although the main process was used, if molecular ions such as SiF'', SiF2+, and 5iF3+ are used as the ion species, the effects of the present invention can be achieved even with a single ion implantation process.
Regarding the implantation energy and implantation dose of ions and F ions, as long as F ions give a deeper implanted ion distribution than Si ions, the effects of the present invention can be obtained even if conditions other than the numerical values used in this example are used. Needless to say, you can get the same results.

(Effect of the invention) By using the method of the invention, high g. Accordingly, a III-V semiconductor device that is less affected by the short channel effect can be realized. In particular, by reducing the short channel effect, even in enhancement type III-V semiconductor devices, 500
It becomes possible to realize a high gm of about m5/mm with good controllability.

Note that the n-type active layer of the In-V group semiconductor device according to the present invention contains a large amount of F atoms, the effects of which have not been previously clarified, and there is concern that the presence of F atoms may have an adverse effect on device characteristics. However, there is no significant difference in the degree of photoresponse or hysteresis observed in the DC characteristics of the fabricated field-effect transistor containing F atoms in the active layer compared to those fabricated using conventional methods, indicating that the introduction of F atoms is It has been confirmed that there is no adverse effect on device characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram for explaining the present invention in detail;
FIG. 2 is a diagram for explaining the present invention in detail, and FIG. 3 (
a) to (g) are cross-sectional views showing an example of the present invention in the order of steps, FIG. 4 is a view showing the effects of the present invention, and FIG. 5 is a view showing an example of the implanted ion concentration distribution according to the conventional method. be. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... Photoresist, 3... Si ion, 4... F ion, 5
... n-type operating layer, 6 ... annealing protective film, 7
...Gate electrode, 8...Si ion, 9...
・n+ contact layer, 10..., ohmic electrode, first
Diagram h Seven cow stock certificate aha5
Figure 2 0 0.2 0.4 Depth (pm) Figure 3 Figure 3 Only Figure 4 0.1 0.5 1 23 Gate length
(,Lm)

Claims (1)

[Claims] In the n-type operating region of the III-V semiconductor device, the n
A III-V semiconductor device comprising a fluorine ion implantation region having an implantation distribution depth equal to or greater than the thickness of a mold operating region.