JPS6319073A - Pattern data inspecting device - Google Patents

Abstract

PURPOSE:To attain the processing of the enormous quantity of data at a high speed by detecting the design rule violation of the pattern data with a pipeline processing and processing in parallel respective processings themselves of the pipeline with an array processor. CONSTITUTION:Under an interface part 3, the pattern data and the program of a bit map form are inputted from a successive computer 1 to a buffer memory 2. After the input completion, the pattern data are inputted from the buffer memory 2 to an array processor 4 line by line under the control of a control part 5, the prescribed pattern data are checked and the result is written to the buffer memory 2. Next, after all lines are completed, the successive computer 1 reads the data of the result from the buffer memory 2 under the control of the interface part 3 again, and the successive computer 1 prepares the document of the inspecting report and the drawing based upon the data of the result.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pattern data inspection device that detects a violation of design rules in pattern data of an LSI or VLSI mask or direct exposure.

(Prior Art and Problems to be Solved by the Invention) Design rules for mask or direct exposure pattern data include the batten width, the width of the space between battens, etc. Violation of these rules will significantly reduce the manufacturing yield of LSI and VLSI. Therefore, it is necessary to check in advance whether the pattern data violates the design rules.

By the way, more than ten types of masks are normally used to manufacture one type of LSI or VLSI, and each mask is called an n-th layer (n=0, 1, 2, etc.) mask.
It consists of many two-dimensional figures such as rectangles and polygons.

These two-dimensional figures have dimensions and intervals that are integral multiples of the minimum dimension, so when considering a lattice-like space divided by the minimum dimension, the vertices of the two-dimensional figures are always lattice points, as shown in Figure 12. will exist in Therefore, when expressing pattern data, it can be expressed using grid spacing and two-dimensional graphic data (bitmap representation) defined in grid space. For example, when the two-dimensional figure in FIG. 12 is expressed as a bitmap, it becomes as shown in FIG. 13. In addition, “1”
is included in the figure, and "0°" indicates not included in the figure.

On the other hand, a design rule violation refers to a case where the width of a figure or the space between figures on these bitmaps or a bitmap generated based on these bitmaps is less than a specified value.

Conventionally, detection of such violations has been sequentially processed by a sequential computer, or a dedicated device has been considered.

However, in the case of a sequential computer, figures are handled as vectors, but in this case, for example, if we design a chip with a minimum dimension of 025 μm and a side of 16 mm, the amount of data will reach several million vectors, so the processing time will be It is only a simple inspection that ignores the effect on the design rules of adjacent patterns (for example, as shown in Figure 12, subtle changes such as widening the space adjacent to a thick wiring and narrowing the space adjacent to a thin wiring). The drawback was that it couldn't be done.

Furthermore, the following three systems and their devices are known as dedicated devices.

■Window processor method ■FAST MASK method ■O8L method However, as shown in FIG. The data is sent to the two-dimensional array processor arranged in step 4), and a matching calculation is performed on the two-dimensional array processor with a separately prepared reference figure, thereby locally detecting a violation of design rules.

(References; L, 5eiler, “A Hardwa
ressistedDesign Ru1e C
heck Architecture”, Proc.
, 19th Design Automation
Conf., June 1982. pp232-23
8) Furthermore, the FAST MASK method (2), as shown in FIG. 15, consists of a plurality of microprocessors, and detects design rule violations by determining the mask layer that each microprocessor is responsible for. (References; S,
Macon+ber,et,al,“Hard-war
e Acceleration For Layout
Verification”.

Vl, SI 11esign, June 1985. p
pl8-27) In addition, as shown in FIG. 16, the O3L method (2) is a hardware version of the algorithm that has conventionally been performed sequentially on a computer, and handles pattern data as vector data and performs WL and MRL.

Three FIFOs called MVL (memory with first-in, first-out function) and a control unit 1 that controls input/output to this memory.
Consists of 0P, VS, OP, and DC.

(Reference: Miki et al., “Study of layout design verification algorithm and hardware architecture to realize it”, IEICE technical report, CAS85-163゜ppl-8) Here, we will discuss practical problems, for example, when the minimum size is 0. If we consider the case where a chip of 25 μm and 18 mm on a side is designed, the pattern data will be data in bitmap format in the range (o, o) to <216, 216), which will be a huge number.

However, the window processor method (2) has a drawback in that the parallelism of processing is low, and therefore high-speed processing cannot be expected. In addition, the two-dimensional array processor
Increasing the size of the dimensional array requires correspondingly increasing the number of reference patterns, so increasing the size of the two-dimensional array to 4×4 or more is practically undesirable and involves great difficulty.

Furthermore, in the 0FAST MASK method, each microprocessor corresponds to each mask layer, so there is a drawback that at most only the mask layer can be sped up.

In addition, in the O8L method (■), like the method using a sequential computer, an inspection is performed that ignores the influence of adjacent patterns, and
This method uses a method to numerically calculate the distance in the diagonal direction and the spacing between parallel wires from straight line equations, and this process is sequentially processed by a microprocessor, which has the drawback of making it difficult to increase the speed.

As described above, there are various problems with the conventional technology, including the difficulty of handling a huge amount of data described in a large coordinate space and performing high-speed inspections that take into account the influence of adjacent patterns on the design rules. It had

(Means for Solving the Problems) The present invention has been proposed in view of the above points, and its purpose is to inspect design rule violations of mask or direct exposure pattern data of LSI etc. It is an object of the present invention to provide a pattern data inspection device that has a simple configuration and can process at high speed.

In order to achieve the above object, the present invention provides a device for inspecting design rule violations of mask or direct exposure pattern data of LSI etc., which includes a buffer memory for storing pattern data in bitmap format sequentially inputted from a computer, and a logical operation. - A play processor that has a configuration in which a plurality of processing elements capable of performing operations such as addition, subtraction, and multiplication are interconnected and can be configured as a one-dimensional array by mode setting, and a control unit that controls data transfer between the play processor and the buffer memory. and after inputting bitmap format data of one line of the pattern data or a part thereof to the array processor, the array processor operates as a one-dimensional array processor, and the data of each processing element or an adjacent processing element is held. Generate bitmap data corresponding to the inspection item from the bitmap data group, and change the width of the figures included in the generated bitmap data and the spacing between the figures to the adjacent processing elements in the direction parallel to the input line. This is calculated by using the data transfer and arithmetic functions of the processing elements, and in the direction perpendicular to the input line, the bitmap format data previously generated held by each processing element is also used. For directions diagonal to the input line, it is determined by calculation that each processing element is the lower left corner point, lower right corner point, upper left corner point, upper right corner point, and other adjacent processing elements. After recognition from the bitmap data generated by The gist of this invention is a pattern data inspection device characterized by:

(Example) Next, an example of the present invention will be described. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a block diagram showing an embodiment of the pattern data inspection device of the present invention, in which 1 is a sequential computer, 2 is a buffer memory, 3 is an interface section, 4 is an array processor, and 5 is a buffer memory 2 and an array. This is a control unit that controls the processor 4. Further, 6 and 7 are data lines, and 8 is a control signal line.

Its operation is to sequentially input bitmap format pattern data and programs from the computer 1 to the buffer memory 2 under the control of the interface section 3, and after the input is completed, the data are input from the buffer memory 2 under the control of the control section 5. The operation of inputting pattern data one line at a time to the array processor 4, checking the predetermined pattern data, and writing the result into the buffer memory 2 is performed for all lines.

Note that a line refers to one horizontal column of data in bitmap format as shown in FIG. 13 and the like. Then, after all lines are finished,
Again under the control of the interface section 3, the sequential computer 1 reads the result data from the buffer memory 2, and the sequential computer 1 creates an inspection report document or drawing based on the result data.

Next, FIG. 2 shows the configuration of the array processor 4 in FIG. 1. Therefore, array processor 4 has 1
BIT processing elements (PE) 101-11
6 are arranged in two dimensions, and each processing element is connected to adjacent processing elements in four directions. Note that the rightmost processing element is connected to the leftmost processing element of the next stage.

Further, the individual processing elements are connected to selection circuits 201, 202, 208, . . . as shown in FIG. register 203
．． 205.2-bot RAM 204. ALU 207
° Consists of a control circuit 209. Selection circuit 201.202.
The register 203 has the role of exchanging data with adjacent processing elements. ALU 207 is used to perform logical operations, addition, subtraction, and multiplication. 2 baud)
RAM 204 is for data storage, and buffer memory 2
In addition to one line worth of pattern data sent from , various intermediate data.

Used to temporarily store design rule judgment results, etc. The register 205 along with the control circuit 209 provides a common fldJ all signal 125 to all processing elements.
It has the role of locally modifying each processing element.

Since the array processor 4 has such a structure, when data is sent in the vertical direction in FIG. can be done quickly. During data processing, the array processor 4 is in one-dimensional array processor mode (101.102.103.., 104.105 in FIG. 2).
．． 106.107°-2108,109,110,11
1, -, 112, . . . 116, which becomes one-dimensional.

) works.

The array processor 4 then creates one line of intermediate data that matches the inspection item.

Inspection of the slam width in the X direction (direction parallel to the line).

Inspection of the slam width in the X direction (direction perpendicular to the line).

This allows inspection of the width of the baton in the diagonal direction.

Further, the method of outputting the result differs depending on the determination result, but this can be realized by locally modifying the control signal by the register 205 and the control unit @ 209 in the processing element.

Next, the operation of checking pattern data for violation of design rules will be specifically explained.

Figure 4 shows a flowchart of the entire inspection. First, the input for the first line is performed, and all layers of the first line (
Data for all layers of the mask is stored across the processing elements of the array processor 4. Figure 5 shows an example of pattern data, in which (a) shows the pattern data of the 8th layer, (b) shows the pattern data of the second layer, and (c) works as a one-dimensional array processor. This conceptually shows a state in which data of each layer is input to the array processor 4. In addition, in (a) and (b), ``1'''' indicates that it is included in the figure, and ``0゛'' indicates that it is not included in the figure,
The stepped side in (b) indicates that the 45° diagonal side is expressed in grid coordinates as shown.

In FIG. 4, following the input of the above-mentioned data, data in a bitmap format matching inspection item J is generated. In other words, after inputting data, the array processor 4 operates as a one-dimensional array processor in which processing elements corresponding to the number of horizontal bits of the bitmap are arranged in one dimension, and has the function of exchanging data between adjacent processing elements. It has a function to accumulate data in an element, a function to perform logical operations, addition, subtraction, and 2 multiplication. For example, when the inspection item "8th layer slam and no slam in the second layer" is specified,
Bitmap format data C is generated by executing the logical operation c=anT on all processing elements at once. Furthermore, a.

b (data in bitmap format for the a-th layer and the s-th layer, respectively).

Next, regarding the X-direction slam width inspection in Fig. 4, the sixth
This will be explained using figures. In addition, it is set as D-4 in the design rule "bang width is D or more" in the X direction. Therefore, in FIG. 6, the generated bitmap data (a) to be checked is
This is data generated as bitmap format data that matches inspection item J in FIG. β is data indicating the right end of the “1” region of α, and is the result of shifting 7 to the left by one processing element (I P E) and A.
It is obtained by performing an ND operation. γ is obtained by performing an OR operation of β with β by IPE left shifting D−1 times, and this becomes the reference pattern (convergence D) for inspection. δ
is obtained by a logical operation of γna, and 1'' remains only in the portion that is less than the standard batten width. ε is obtained by performing an OR operation of δ shifted to the right by IPE and δ D-1 times.

By performing an AND operation on ε and α, only the processing element corresponding to the violation pattern data becomes "1'", and a violation can be detected from this result.

Next, the X direction slam width test in FIG. 4 will be explained. Note that D = 4 in the design rule ``pattern width is D or more'' in the When the bitmap data value is "1", counting "°1" is started. For example, if FIG. 5(a) is used as generated bitmap data, the values of each processing element after inputting the seventh line are 1.1.1.1°1, 0, . 0,
O, 0, 0, 0, 0. Then, move to the next line, and the value of the generated bitmap data of the previous line is “1”.
The value of the generated bitmap data for this line is also “1”.
When , continue counting "1". In other words, Fig. 5 (
In b), the value of each processing element after inputting the 8th line becomes 2.2.2.2.2.0.0.0.0.0.0.0. Then, it moves to the next line, and when the value of the generated bitmap data of the previous line is "1" and the value of the generated bitmap data of the current line is "0", the count is stopped and the previous value is The size is compared with D, and if it is smaller, it is determined that there is a violation of the design rules.In other words, in this example, the slam width in the X direction on the 7th and 8th lines is detected as 2, which is smaller than D (=4), so it is a violation. It is determined that

Next, the diagonal slam width test (diagonal design rule "bang width is D or more") in FIG. 4 will be explained.

FIG. 7 shows a processing flow. Processing is performed according to this flow, and first, type classification is performed in each processing element. Type classification is performed according to the criteria shown in FIG. 8, and the results are stored in each processing element. As for the type, as shown in Figure 8 (a), "value of own current line, value of current line of processing element adjacent to the right.

Both the values of its previous line are °゛1”, and the value of the previous line of the processing element adjacent to the right is “
0''' processing element is called type A.

As shown in Figure 8 (b), [the value of the current line of the current line, the value of the current line of the processing element adjacent to the left, and the value of the previous line of the self are all 1'', and the value of the processing element adjacent to the left is The value of the previous line is "0"
This processing element is called type B. Figure 8 (
As in c), “If the value of your current line is “0”′,
A processing element in which the value of the current line of the processing element adjacent to the right, the value of its previous line, and the value of the previous line of the processing element adjacent to the right are "1'" is referred to as type C. As shown in Fig. 8 (d), "the value of the current line of itself is ``0'''', and the value of the current line of the processing element adjacent to the left,
Value of own previous line.

A processing element in which the value of the previous line of the processing element adjacent to the left is "1" is called type D.

Next, as shown in FIG. 7, labeling is performed in each processing element. That is, for a type A processing element, the label of the processing element is (0, 0, 0). For a type B processing element, the label of the processing element is (0, 0, 1). If a processing element has an empty label and the label in the previous line is (k, j, m), the label of the processing element is set to (k, l+1, m). A processing element with an empty label whose label in the current line of the right adjacent processing element is (
k, l.

0), then set the label of the processing element to (
k+1. l, 0). If it is a processing element with an empty label and the label of the left adjacent processing element in the current line is (k, l, 1),
The label of the processing element is (k+1.l,
1).

FIG. 9 shows an example of labeling. When the fifth line is input, the labels are labeled in the order of (a) and (b), when the sixth line is input, the labels are labeled in the order of (c) and (d), and the seventh line is labeled in the order of (c) and (d). (E) during line input.

(to) and stored in the processing element.

In Figure 10, the dimension of the constriction of a figure with a constriction is -20=, and in Figure 11, the distance between the hypotenuses of a figure with two parallel hypotenuses (45°) is greater than or equal to the specified value "'D"'. This shows an example of testing whether or not the
, Figure 11 (a) shows the pattern data to be inspected,
FIG. 10(B) and FIG. 11(B) respectively show the results of labeling performed sequentially from the bottom side. In addition, the 10th
Figures (A) and 11 (A) also show the results of the type classification according to Figure 8. Note that FIG. 9 described above shows the progress of labeling with respect to FIG. 10.

As a result of labeling, the bits of type C in Figure 10 (b) are labeled (5, 3, 0), and the bits of type C in Figure 11 (b) are labeled (5°4.0). ) is attached. In the case of FIG. 10, the distance between the constrictions corresponds to the distance between the type A bit and the type C bit.

In this case, the distance is calculated when a bit of type C is processed, and its label is (x, YpZ), then 82
+, 2 is the distance. However, instead of finding the distance as a numerical value, it is sufficient to judge the magnitude relationship with D, so in reality, instead of 7=+y'<D, x2+y2<
D2 is calculated, and when it is satisfied, it is determined that the design rule is violated. On the other hand, in the case of Figure 11, the distance between the parallel hypotenuses is given by the type C bit label (XeV, Z)
When m<o, that is, x2+y2<D2, it is determined that there is a violation of the design rule.

In addition, in the above explanation, the method for detecting a violation of the design rules for the width of the button was described, but if the ground (background) and the button are reversed, the width of the ground (i.e., the spacing between figures) can also be detected using the same method. It is clear that design rule violations can be detected.

In addition, although the above explanation describes the design rule violation detection method, it is possible to use this design rule violation detection method to detect violation locations and make corrections to comply with the design rules based on the results. is clear.

As described above, the present invention provides a method of inputting bitmap format data line by line from one direction to an array processor, detecting and outputting design rule violations in synchronization with the input, and a method in which the array processor calculates the bat width in the diagonal direction. to recognize the corner points on the top and bottom sides of the pattern, and move from the bottom corner point to the top corner point (x
.

This technique differs greatly from conventional techniques in that it performs two labels (y) and determines that the upper side corner point is in violation of the design rules based on the label (xty) and a separately given reference value.

Furthermore, since the present invention inputs and processes one line at a time, there is no limit to the number of lines in the X direction. In addition,
It goes without saying that an X-direction mesh larger than the number of processing elements of the array processor can be processed by division.

Furthermore, it goes without saying that when input data contains consecutive lines with the same content, the amount of input data can be reduced by using control data.

In addition, regarding inspection of pattern data using design rules that take into account the influence of adjacent patterns, vertical and diagonal inspections are processed line by line sequentially, so design rules that reflect input data can be updated at any time. Based on the design rules that can be applied and reflect the unentered data (inspection becomes possible once the unentered data has been entered. Also, for the horizontal direction, the design rules that reflect the entered data at any time) It is clear that it can be applied.

(Effects of the Invention) As described above, according to the present invention, violation of design rules in mask or direct exposure pattern data is detected by so-called pipeline processing, in which each line is input and processed, and pipeline processing is performed. Since each process itself is processed in parallel by a play processor that operates as a one-dimensional array processor, it has the effect of processing a huge amount of data at extremely high speed. Furthermore, by using pattern data in a bitmap format and processing it by assigning one processing element to each bit, it is possible to extract features of the pattern data. direction,
This has the effect of being able to extremely efficiently calculate design rule violations such as the width of patterns in diagonal directions and the width of diagonal figures.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the pattern data inspection device of the present invention, FIG. 2 is a block diagram of the array processor in FIG. 1, FIG. 3 is a block diagram of the processing element in FIG. 2, and FIG. FIG. 5 is an explanatory diagram of the inspection process according to the present invention. FIG. 6 is an explanatory diagram of the X-direction pattern width inspection according to the present invention. FIG. 7 is a diagonal pattern width inspection. Fig. 8 is an explanatory diagram of type classification in diagonal pattern width inspection, Fig. 9 is an explanatory diagram of labeling in diagonal pattern width inspection, and Fig. 10 is a diagram of the width of the constriction of a constricted figure. An explanatory diagram of the calculation, Fig. 11 is an explanatory diagram of the calculation of the hypotenuse interval of a figure having two parallel hypotenuses (45°), Fig. 12 is a diagram showing an example of a pattern based on a design rule that takes into account the influence of adjacent patterns,
Figure 13 is a bitmap representation of Figure 12, and Figure 14 is a bitmap representation of Figure 12.
The figure is a block diagram of the window processor, and Figure 15 is FAS.
The configuration diagram of T MASK, and FIG. 16 is a configuration diagram of O8L. 1... Sequential computer, 2... Buffer memory,
3...Interface unit, 4...Array processor, 5...Control unit, 6, 7...Data line, 8...
... Control wholesale signal line patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Toshio Takayama and one other person 飄■ and Shurou Tsuyoshi (1) M 糎

Claims (1)

[Claims] In a device that inspects design rule violations in mask or direct exposure pattern data such as LSI, it has a buffer memory that stores bitmap format pattern data sequentially input from a computer, and can perform operations such as logical operations, addition/subtraction, and multiplication. It has an array processor that has a configuration in which a plurality of processing elements are interconnected and can become a one-dimensional array by mode setting, and a control unit that controls data transfer between the array processor and the buffer memory, After inputting data in bitmap format of one line of data or a portion thereof, operating the array processor as a one-dimensional array processor;
Generates bitmap format data corresponding to the inspection item from the bitmap format data group held by each processing element or adjacent processing elements, and the width of the shapes and the spacing between the shapes included in the generated bitmap format data. In the direction parallel to the input line, it is calculated by using the data transfer using the connection of adjacent processing elements and the calculation function of the processing element, and in the direction perpendicular to the input line, it is calculated by the data stored in each processing element. It is obtained by calculation using previously generated bitmap format data, and for directions diagonal to the input line, each processing element is the lower left corner point, lower right corner point,
After recognizing the upper left corner point, upper right corner point, and other points from the bitmap data generated by each processing element and adjacent processing elements, label the lower left corner point and lower right corner point separately in the horizontal and vertical directions. A pattern data inspection device characterized by calculating the sum of squares of labels in each processing element and processing these in parallel.