JPS6319095B2 - - Google Patents
Info
- Publication number
- JPS6319095B2 JPS6319095B2 JP56153893A JP15389381A JPS6319095B2 JP S6319095 B2 JPS6319095 B2 JP S6319095B2 JP 56153893 A JP56153893 A JP 56153893A JP 15389381 A JP15389381 A JP 15389381A JP S6319095 B2 JPS6319095 B2 JP S6319095B2
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- phase
- circuit
- signal
- vco
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
本発明は発振回路、特に位相同期形高安定発振
回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit, and particularly to a phase-locked highly stable oscillation circuit.
周波数1の基準信号を用いて、これに位相同期
した高安定な周波数2の発振出力を得るというこ
とはしばしば行なわれる。そしてこの種の用途に
供するのが本発明で言及する位相同期形の高安定
な発振回路である。この発振回路は、後述するよ
うに電圧制御形発振器（VCO）を含んでフエー
ズロツクループ（PLL）を形成するものである
が、不都合な問題を伴うことがしばしばある。こ
の不都合な問題とは位相同期引込みに異常に長い
時間、例えば約１時間、を要することである。こ
のような問題を生じた理由は高安定な前記VCO
を用いたからに他ならない。なぜなら、高安定な
VCO程、制御入力電圧（Ｖ）対発振出力周波数
（）の関係が穏やかであるからである。つまり、
制御入力電圧（Ｖ）を大きく変化させても発振出
力周波数の方がそれ程大きく変化してくれないの
である。それなら前記（Ｖ）対（）の関係が鋭
敏なVCOを利用することにより前述した問題が
解決される、という考え方が成り立つ。ところ
が、このような（Ｖ）対（）の鋭敏なVCOは
逆に安定度の悪いVCOであるのが一般的であり、
本発明が意図している高安定発振回路を構成する
ためのVCOとしては不適当である。 It is often done to use a reference signal of frequency 1 to obtain a highly stable oscillation output of frequency 2 that is phase-synchronized with this reference signal. The highly stable phase-locked oscillation circuit referred to in the present invention is suitable for this type of use. This oscillation circuit includes a voltage controlled oscillator (VCO) to form a phase lock loop (PLL), as will be described later, but is often accompanied by inconvenient problems. The disadvantage of this is that phase synchronization takes an unusually long time, for example about an hour. The reason for this problem is the highly stable VCO.
This is only because we used . Because it is highly stable
This is because the relationship between the control input voltage (V) and the oscillation output frequency () is gentler as the VCO increases. In other words,
Even if the control input voltage (V) is changed greatly, the oscillation output frequency does not change that much. Then, the idea is that the above-mentioned problem can be solved by using a VCO with a sensitive relationship between (V) and (). However, such a VCO with a sharp (V) vs. () ratio is generally a VCO with poor stability.
It is unsuitable as a VCO for configuring the highly stable oscillation circuit intended by the present invention.
従つて本発明の目的は、高安定なVCOを用い
ながら、位相同期引込み時間は従来より大幅に短
縮可能な位相同期形で高安定な発振回路を提案す
ることである。 Therefore, an object of the present invention is to propose a highly stable phase-locked oscillation circuit that uses a highly stable VCO and can significantly shorten the phase-locking pull-in time compared to the conventional one.
上記目的に従い本発明は、位相同期引込み状態
に至るまでフエーズロツクループ内に強制的に大
きな位相外れ状態を生じさせるようにしたことを
特徴とするものである。 In accordance with the above object, the present invention is characterized in that a large out-of-phase state is forcibly caused within the phase lock loop until the phase locking state is reached.
第１図は一般的な位相同期形且つ高安定な発振
回路の構成を示すブロツク図である。本図におい
て、V1は基準信号であり、周波数1の高安定な
基準発振信号である。V2が求める信号であり、
基準信号V1に位相同期した周波数2の発振出力
信号である。この発振出力信号V2を送出するの
は、電圧制御形発振器（VCO）１４である。
VCO（Voltage Controlled Oscillator）１４は低
域ろ波フイルタ（LPF）１３を介して位相差検
出器１２からの出力信号を受信し、これをもつて
電圧制御入力とする。この電圧制御入力は、信号
V1と信号V2の間の位相差に比例した入力であ
り、該位相差に比例したレベルの電圧（Ｖ）で
VCO１４の発振出力周波数（）を変化させる。
この位相差は前記位相差検出器（PD：Phase
Detector）１２によつて検出される。このため
に該位相差検出器１２は、第１分周器（分周比
n1）１１を通した基準信号V1と、第２分周器
（分周比n2）１５を通した発振出力信号V2を入
力とし、両者の位相差を検出する。この位相差が
零に収れんしたところで、信号V2は信号V1に
位相同期したことになる。ここに、いわゆるフエ
ーズロツクループ（PLL）が形成される。 FIG. 1 is a block diagram showing the configuration of a general phase-locked and highly stable oscillation circuit. In this figure, V 1 is a reference signal, which is a highly stable reference oscillation signal with a frequency of 1 . V 2 is the desired signal,
This is an oscillation output signal with a frequency of 2 that is phase synchronized with the reference signal V1 . A voltage controlled oscillator (VCO) 14 sends out this oscillation output signal V2 .
A VCO (Voltage Controlled Oscillator) 14 receives the output signal from the phase difference detector 12 via a low-pass filter (LPF) 13, and uses this as a voltage control input. This voltage control input is the signal
It is an input proportional to the phase difference between V 1 and signal V 2 , and the voltage (V) is at a level proportional to the phase difference.
Change the oscillation output frequency () of VCO14.
This phase difference is detected by the phase difference detector (PD).
Detector) 12. For this purpose, the phase difference detector 12 has a first frequency divider (frequency division ratio
The reference signal V 1 passed through n1) 11 and the oscillation output signal V 2 passed through the second frequency divider (dividing ratio n2) 15 are input, and the phase difference between the two is detected. When this phase difference converges to zero, the signal V 2 becomes phase-locked with the signal V 1 . Here, a so-called phase lock loop (PLL) is formed.
ところで、既述したように、VCO１４として
非常に高安定なVCOを用いると前記の電圧（Ｖ）
対周波数（）の関係は非常に穏やかとなり位相
差がかなり大きいにも拘らず発振出力周波数はそ
れ程大きくは変化してくれない。この結果、位相
同期引込みに異常に長い時間を要するということ
がしばしば生ずる。一般に位相同期引込み時間Ｔ
は
Ｔ＝Ｋ／Gυ（Vs−Vo）／Ｎ
で表わすことができる。ただし、Ｎ：第２分周器
の分周比（n2），Ｋ：位相差検出器１２における
信号入力時の２入力の位相差（rad），G〓：VCO
１４の利得（rad／sec・Ｖ），Vs：入力信号断時
のVCO１４の入力電圧（Ｖ），V0：同期時の
VCO１４の入力電圧（Ｖ）である。 By the way, as mentioned above, if a very highly stable VCO is used as the VCO 14, the voltage (V)
The relationship with respect to frequency ( ) is very gentle, and the oscillation output frequency does not change that much even though the phase difference is quite large. As a result, phase locking often takes an unusually long time. In general, phase synchronization pull-in time T
can be expressed as T=K/Gυ(Vs-Vo)/N. However, N: frequency division ratio of the second frequency divider (n2), K: phase difference between two inputs at the time of signal input to the phase difference detector 12 (rad), G〓: VCO
Gain of 14 (rad/sec・V), V s : Input voltage of VCO 14 (V) when input signal is disconnected, V 0 : When synchronized
This is the input voltage (V) of the VCO 14.
例えば、中心周波数o＝3720kHz，可変特性
Δ＝0.075ppm／ＶのVCOを用いると、Ｎ＝
1000，Vs−V0＝1Vの場合の最大位相同期引込み
時間Ｔは、VCOの利得が
G〓＝2π・Δ・o
＝0.075×10-6×2π×3720×103
＝1.75rad／sec・Ｖ
となることから、
Ｔ＝Ｋ／Gυ（Vs−Vo）／Ｎ＝2π／1.75×１／1000＝
3590.4sec
つまり約59分50秒ということになる。このよう
な長時間を要したのでは非能率極りない。 For example, when using a VCO with center frequency o = 3720kHz and variable characteristic Δ = 0.075ppm/V, N =
1000, the maximum phase synchronization pull-in time T when V s −V 0 = 1V is the gain of the VCO G = 2π・Δ・o = 0.075×10 -6 ×2π×3720×10 3 = 1.75rad/sec・Since V, T=K/Gυ(Vs-Vo)/N=2π/1.75×1/1000=
3590.4sec, which means about 59 minutes and 50 seconds. It would be extremely inefficient if it took such a long time.
第２図は本発明に基づく位相同期形且つ高安定
な発振回路の構成を示すブロツク図であり、第３
図は第２図の回路の動作説明に用いる波形図であ
る。これら第２図および第３図を用いて以下本発
明の構成を説明する。ただし、第２図において、
第１図と同一の構成要素には同一の参照番号又は
記号を付して示す。従つて第２図中の２１，２２
―１，２２―２等のブロツクとそのまわりの結線
が新たに加わつたことになる。２１は位相差判定
回路であり、これに信号瞬断回路２２が付帯す
る。信号瞬断回路２２は基準信号V1を略周期的
に瞬断する回路であり、例えば矩形波発振器２２
―１（非駆動時は“Ｈ”出力を継続して出力する
ようにしてある）と、ANDゲート２２―２をも
つて構成することができる。位相差判定回路２１
は、、位相差検出器１２からの位相差が所定の範
囲（rad）に入つているか否かを判定する。所定
の範囲内にあれば、位相同期引込みがなされてお
り問題がない。ところが所定の範囲外だと判定さ
れたときは、直ちに強制同期引込みを実施しけれ
ばならない。このために、矩形波発振器２２―１
を起動する。この発振出力波形は第３図のｂ欄に
示され、これはさらにANDゲード２２―２の一
方の入力に印加される。するとANDゲート２２
―２は略周期的に開閉し、ａ欄の基準信号
（V1）をｃ欄の如く瞬断する。基準信号を瞬断
することにより、フエーズロツクループ（PLL）
内には強制的に大きな位相外れ状態が生ぜしめら
れる。これにより、PLLの状態は大きく変動せ
しめられる。例えば、当初位相差φであつたも
のが、瞬断t1，t2，t3c欄参照）が入る毎にφ″，
φ′の如く大きなステツプで小さくなり、急速に位
相差零に近づく。位相差が所定の範囲内に入れ
ば、判定回路２１は発振器２２―１を非駆動と
し、“Ｈ”出力がANDゲート２２―２に印加され
続ける。つまり第１図と等価な回路に戻る。な
お、第３図のｄ〜欄の各々における一対のパル
スは、基準信号V1と発振出力信号V2の位相関
係を図解的に表現するために描かれたものであ
り、例えば位相差検出器１２の２入力をそれぞれ
正弦波から矩形波に変換したのち、その立上りを
微分したパルスに相当する。 FIG. 2 is a block diagram showing the configuration of a phase-locked and highly stable oscillation circuit based on the present invention.
This figure is a waveform diagram used to explain the operation of the circuit of FIG. 2. The configuration of the present invention will be explained below using FIGS. 2 and 3. However, in Figure 2,
Components that are the same as in FIG. 1 are designated with the same reference numbers or symbols. Therefore, 21 and 22 in Figure 2
-1, 22-2 etc. blocks and the connections around them are newly added. Reference numeral 21 denotes a phase difference determination circuit, to which a signal instantaneous interruption circuit 22 is attached. The instantaneous signal interruption circuit 22 is a circuit that instantaneously interrupts the reference signal V 1 approximately periodically, and for example, the signal interruption circuit 22
-1 (continuously outputs "H" output when not driven) and an AND gate 22-2. Phase difference determination circuit 21
determines whether the phase difference from the phase difference detector 12 is within a predetermined range (rad). If it is within a predetermined range, phase locking has been achieved and there is no problem. However, if it is determined that it is outside the predetermined range, a forced synchronization pull-in must be performed immediately. For this purpose, the square wave oscillator 22-1
Start. This oscillation output waveform is shown in column b of FIG. 3, and is further applied to one input of AND gate 22-2. Then AND gate 22
-2 opens and closes approximately periodically, and momentarily interrupts the reference signal (V 1 ) in column a as shown in column c. By momentarily interrupting the reference signal, phase lock loop (PLL)
A large out-of-phase condition is forcibly created within the This causes the state of the PLL to change significantly. For example, what was initially a phase difference of φ becomes φ'' every time a momentary interruption t1, t2, t3c (see columns t1, t2, t3c) occurs.
The phase difference decreases in large steps such as φ', and rapidly approaches zero phase difference. If the phase difference falls within a predetermined range, the determination circuit 21 deactivates the oscillator 22-1, and the "H" output continues to be applied to the AND gate 22-2. In other words, the circuit returns to the equivalent circuit shown in FIG. It should be noted that the pair of pulses in each of columns d to 3 in FIG. This corresponds to a pulse obtained by differentiating the rise of each of the 12 inputs from a sine wave to a rectangular wave.
又、第３図のｄ〜欄では位相差がφ→
φ″→φ′と徐々に小さくなる例を示したが、実際
には、全てがこのようにシーケンシヤルに変化す
るとは限らず、あくまでもランダムである。ラン
ダムでありながら、例えば１分も経過すれば、位
相差は所定の範囲に落ち込むであろうことは明ら
かである。つまり、強制的にフエーズロツクルー
プ（PLL）に擾乱を与えながら、所望の小さい
位相差が出現するタイミングを待つ。この擾乱
は、例えば10Hzの割合で与えられる。すなわち矩
形波発振器２２―１は例えば10Hzの発振器とす
る。このようにすれば、最適位相差の形成が迅速
になされ、従来の如く例えば約１時間というよう
な長時間を要することはあり得ない。 Also, in column d~ of Fig. 3, the phase difference is φ→
I showed an example where the size gradually decreases from φ″ to φ′, but in reality, not everything changes sequentially like this, it is just random. Even though it is random, for example, if one minute passes, , it is clear that the phase difference will fall within a predetermined range.In other words, while forcing the phase lock loop (PLL) to be disturbed, we wait for the timing when a desired small phase difference appears.This disturbance is given at a rate of, for example, 10 Hz.In other words, the rectangular wave oscillator 22-1 is, for example, a 10 Hz oscillator.In this way, the optimum phase difference can be formed quickly, for example in about one hour as in the conventional case. It is impossible that it would take a long time.
以上説明したように本発明によれば、高安定で
ありながら位相同期引込み時間を大幅に短縮可能
な位相同期形発振回路が実現される。 As described above, according to the present invention, a phase-locked oscillator circuit that is highly stable and can significantly shorten the phase-locking pull-in time is realized.
第１図は一般的な位相同期形且つ高安定な発振
回路の構成を示すブロツク図、第２図は本発明に
基づく位相同期形且つ高安定な発振回路の構成を
示すブロツク図、第３図は第２図の回路の動作説
明に用いる波形図である。
１２……位相差検出器、１４……電圧制御形発
振器、２１……位相差判定回路、２２―１および
２２―２……基準信号瞬断回路、V1……基準信
号、V2……発振出力信号。
Figure 1 is a block diagram showing the configuration of a general phase-locked and highly stable oscillation circuit, Figure 2 is a block diagram showing the configuration of a phase-locked and highly stable oscillation circuit based on the present invention, and Figure 3. 2 is a waveform diagram used to explain the operation of the circuit shown in FIG. 2. FIG. 12...Phase difference detector, 14...Voltage controlled oscillator, 21...Phase difference determination circuit, 22-1 and 22-2...Reference signal instantaneous interruption circuit, V1 ...Reference signal, V2 ... Oscillation output signal.
Claims (1)
出する電圧制御形発振器と、前記基準信号と前記
発振出力信号との間の位相差を検出して前記電圧
制御形発振器の電圧制御入力とし且つ該電圧制御
形発振器と共にフエーズロツクループを形成する
位相差検出器とを有してなる位相同期形の発振回
路において、 前記位相差検出器からの位相差が所定の範囲を
超えたか否かを判定する位相差判定回路と、前記
位相差が前記所定の範囲内に入つたことが該位相
差判定回路によつて判定されるまで、前記基準信
号を略周期的に瞬断する信号瞬断回路とをさらに
付加したことを特徴とする発振回路。[Claims] 1. A voltage controlled oscillator that sends out an oscillation output signal whose phase should be synchronized with a reference signal; In a phase-locked oscillation circuit having a phase difference detector as a voltage control input and forming a phase lock loop with the voltage-controlled oscillator, the phase difference from the phase difference detector falls within a predetermined range. a phase difference determination circuit that determines whether or not the phase difference has exceeded the predetermined range; and a phase difference determination circuit that momentarily interrupts the reference signal approximately periodically until the phase difference determination circuit determines that the phase difference is within the predetermined range. An oscillation circuit further comprising a signal instantaneous interruption circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56153893A JPS5856535A (en) | 1981-09-30 | 1981-09-30 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56153893A JPS5856535A (en) | 1981-09-30 | 1981-09-30 | Oscillation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856535A JPS5856535A (en) | 1983-04-04 |
| JPS6319095B2 true JPS6319095B2 (en) | 1988-04-21 |
Family
ID=15572410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56153893A Granted JPS5856535A (en) | 1981-09-30 | 1981-09-30 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856535A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100239121B1 (en) * | 1996-09-06 | 2000-01-15 | 구자홍 | Structure of dome speaker system of video display device |
| KR20210096199A (en) * | 2019-12-26 | 2021-08-04 | 가부시키가이샤 아루박 | film forming device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411419A (en) * | 1987-07-03 | 1989-01-17 | Anritsu Corp | Frequency synthesizer |
| JPH02246620A (en) * | 1989-03-20 | 1990-10-02 | Advantest Corp | Phase locked loop circuit including frequency converter |
-
1981
- 1981-09-30 JP JP56153893A patent/JPS5856535A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100239121B1 (en) * | 1996-09-06 | 2000-01-15 | 구자홍 | Structure of dome speaker system of video display device |
| KR20210096199A (en) * | 2019-12-26 | 2021-08-04 | 가부시키가이샤 아루박 | film forming device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5856535A (en) | 1983-04-04 |
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