JPS63193733A - Code error detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a code error alarm output without dispersion, by providing a majority circuit which inputs a code error alarm signal having the shift outputs of N-stages and a hysteresis characteristic, and outputs the error code alarm signal having the hysteresis characteristic when a value arrives at a prescribed value less than N. CONSTITUTION:The code error alarm signal from a protecting circuit B is inputted to a shift register C of N-stages, and the N shift output of the shift register C of N-stages is connected to a part of the input of the majority circuit E, and the code error alarm signal having the hysteresis characteristic outputted from the majority circuit E is connected to the remaining part of the input of the majority circuit E. For example, assuming the inputs of the N-stages to the majority circuit E as (20), a desicion value as (10), and the feedback input M of the alarm output as (6), and when the code error alarm signal goes to (3), the input of the majority circuit goes to (9), therefore, it goes to an alarm non-detecting output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a code error detection circuit in PCM transmission.

(Prior Art) Conventionally, the output of a code error detection circuit has been used for code error alarm in PCM transmission.

FIG. 4 is a block diagram showing the configuration of a conventional code error detection circuit.

In the figure, the code error υ detection circuit S2 is a timer circuit,
It consists of a code error counting circuit and a protection circuit B.

The timer circuit generates a clock signal 5 with a repetition period T and sends it to the code error counter circuit A and the protection circuit B.

The code error counting circuit A counts the number of pulses of the code error pulse signal l (a signal having the number of pulses corresponding to the number of transmission path code errors) at intervals of 1 hour T, and when the number is m or more, an overflow signal 2 is generated. is generated and sent to protection circuit B.

The protection circuit B outputs a code error detection signal 7 having no hysteresis characteristic when the overflow signal 2 is detected one time in succession.

The probability P that the υ1 code error detection signal 7 is sent by the above operation is given by the following equation since the probability of occurrence of a transmission line code error within time T is Poisson distribution.

(However, To<T, ε(1) where To is the period of the transmission line signal, T is the period of the clock signal output of the timer circuit, and ε is the bit error rate 5m on the transmission line is the overflow threshold of the bit error counting circuit. n indicates the number of protection stages of the protection circuit.

(2) The relationship between the equations is illustrated in Figure 5.

When ε〈εl, it becomes O in P, and the sign error υ detection signal 7, which has no hysteresis characteristic, is not sent out at all, and ε〉ε2
In this case, the code error detection signal 7ij, which does not have a hysteresis characteristic like PK1, is always sent out.

However, when 11<e ε2, O<P<1 and hysteresis characteristic? If the code error detection signal 7 that does not have the code error detection signal 7 is sent out as time passes, or if it is not sent out, the number increases.

(Problem to be Solved by the Invention) Therefore, when the code error detection signal 7 is used as a full alarm output and used as a control signal, for example, a loopback switching control signal in a loop type local area network, the code error rate ε on the transmission path is constantly ε1×ε2
When this is the case, the loopback switching control fluctuates over time, resulting in the entire loose local area network being in a state of disarray.

SUMMARY OF THE INVENTION An object of the present invention is to provide a code error detection circuit which can use a code error detection signal outputted by itself as a good switching signal.

(Means for solving the problem 'ft) To achieve the above object, the code error detection circuit according to the present invention uses a timer for generating tarock pulses, counts all the code error errors for each period of the clock pulse, and calculates the total number of code errors to a predetermined value. a code error counting circuit that outputs an overflow signal when the overflow signal is reached; a protection circuit that outputs a full code error alarm signal when a predetermined number of consecutive overflow signals are detected; and a protection circuit that outputs a full code error alarm signal when the overflow signal is detected; an 8-stage shift register that inputs the shift output of the N stages and a code error g-sum signal having hysteresis characteristics, and outputs a code error alarm signal having the hysteresis characteristics when a predetermined value smaller than N is reached. It consists of a majority circuit.

(Actual flow side) The present invention will be explained in more detail below with reference to one drawing.

FIG. 1 is a block diagram showing an embodiment of a code error detection circuit according to the present invention.

In the figure, the same circuits and signal lines as in FIG. 4 are given the same reference numerals. The code error 9@ signal from the protection circuit B is input to the N-stage shift register C, and the N-shift output of the N-stage shift register C is connected to a part of the input of the majority circuit E.

A code error alarm signal having a hysteresis characteristic outputted from the majority circuit E is connected to a portion of the remaining inputs of the majority circuit E.

FIG. 2 is a diagram showing the relationship between the code error detection probability P and the transmission line code error rate ε.

9@The code error detection tOf3 characteristic when the output 6 is abnormal is shown by the dashed line, and is 0.ε≧ε1-2 in ε≦εIJ″t′P.
This makes him 1st in P.

In addition, the sign error υ detection Ithl characteristic when the e-export power is normal is
It is shown by a solid line, and when e≦'2-1, O0 is in P, and when ε≧ε2-2, it is 1 in P. Also, ε1-1 and ε1-2 are ε1-1〉
It has the relationship ε2-2.

Next, the operation of the circuit of the present invention will be explained.

The code error alarm signal ratio cuff without hysteresis characteristic obtained through the code error counting circuit A and the protection circuit B is N
It is collected through the stage shift register C for N periods of the timer D, and is input to the majority circuit E along with M feedback alarms 4 from the current bulletin output 6, and the result is output as a new soybean compensation signal ratio 6. .

FIG. 3 is a diagram showing the relationship between the transmission code error rate ε and the alarm signal 6.

■→■ When the code error state changes to the code state
After the process of →■→■, a code error is not detected and the output goes from a state with no code error to a code error state, when ■→
After the process of ■→■→■, a code error detection output is obtained.

As a result of the above operations, the alarm output 6 has hysteresis characteristics.

Here, the operation will be explained using specific numbers.

For ease of explanation, N stages of input '1r to the majority circuit
20J, and the judgment value is "10".

Also, the feedback input M' (ir 6 J) of the 1g signal output 6 is given.

When the code error 9 report signal appears in 10 or more of the 20 shift outputs, the majority circuit E outputs an alarm detection output, so the value of the entire input of the majority circuit E becomes xo+6-rx64. In this state, even if the number of code error alarm signals among the 20 shift outputs decreases to "4", it becomes 4+6-rlOJ, and the t-axis output 6 is maintained up to this point. However, when the code error alarm signal becomes "3", the majority circuit input becomes "9".
”, the g-report non-detection output will be obtained.

(Effects of the Invention) As described above, according to the present invention, there is an effect that a code error reporting output without fluctuation can be obtained regardless of the transmission line code error rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a code error detection circuit according to the present invention, FIG. 2 is a diagram showing code error detection probability characteristics of the present invention, and FIG. 3 is a code error versus transmission code error rate e. FIG. 4 is a block diagram of a conventional code error detection circuit, and FIG. 5 is a diagram showing code error detection probability characteristics of the conventional code error detection circuit. 8 l, S 2-... Code error detection circuit A... Code error counting circuit B... Protection circuit C... 8-stage shift register D... Timer E... Majority circuit 1
...Clock error pulse 2...Overflow signal 3...N-stage code error alarm signal 4...Feedback alarm input 5...Cronk pulse signal 6...Code error alarm signal output with hysteresis characteristics F... sign error without hysteresis characteristic be reward ratio output Applicant NEC Corporation agent Patent attorney Inoro Part 5 ε1 ε2 (ε1 × ε2)

Claims (1)

[Claims] a timer that generates a clock pulse; a code error counting circuit that counts code error pulses every cycle of the clock pulse and outputs an overflow signal when a predetermined value is reached; a protection circuit that outputs a code error alarm signal when detected; an N-stage shift register that shifts the code error alarm signal by N stages; and inputs the shift output of the N stages and a code error alarm signal having hysteresis characteristics; A code error detection circuit in PCM transmission comprising a majority circuit that outputs a code error alarm signal having the hysteresis characteristic when a predetermined small value is reached.