JPH0214153U - - Google Patents

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Publication number
JPH0214153U
JPH0214153U JP9119488U JP9119488U JPH0214153U JP H0214153 U JPH0214153 U JP H0214153U JP 9119488 U JP9119488 U JP 9119488U JP 9119488 U JP9119488 U JP 9119488U JP H0214153 U JPH0214153 U JP H0214153U
Authority
JP
Japan
Prior art keywords
input
output port
timing
receiving side
transmitting side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9119488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9119488U priority Critical patent/JPH0214153U/ja
Publication of JPH0214153U publication Critical patent/JPH0214153U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る入出力ポートの一実施例
のブロツク図、第2図は第1図に示す入出力ポー
トの具体的な構成例を示す図、第3図a乃至dは
第1図、第2図に示した入出力ポートの動作を説
明するためのタイムチヤート、第4図は従来の入
出力ポートのブロツク図、第5図a乃至dは第4
図に示した入出力ポートの動作を説明するための
タイムチヤートである。 1……入出力ポート、2……ハンドシエーク制
御部、3……リード/ライト制御部、4……リー
ド/ライト制御回路、5,6……タイミング制御
回路、7……ラツチ回路、8……デコーダ、51
……送信側、52……受信側、STB,STB′
,MREQ,MREQ′……ストローブ信号、B
USY′……ビジイ信号、ACK′……アクノレ
ツジ信号。
FIG. 1 is a block diagram of one embodiment of the input/output port according to the present invention, FIG. 2 is a diagram showing a specific configuration example of the input/output port shown in FIG. 1, and FIGS. 2, a time chart for explaining the operation of the input/output port shown in FIG. 2, FIG. 4 is a block diagram of a conventional input/output port, and FIGS.
3 is a time chart for explaining the operation of the input/output ports shown in the figure. 1... Input/output port, 2... Handshake control section, 3... Read/write control section, 4... Read/write control circuit, 5, 6... Timing control circuit, 7... Latch circuit, 8... decoder, 51
...Sending side, 52...Receiving side, STB, STB'
, MREQ, MREQ'...Strobe signal, B
USY'...busy signal, ACK'...acknowledge signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信側から受信側へのデータの転送をハンドシ
エーク制御によつて行なう入出力ポートにおいて
、送信側および/または受信側とのインタフエー
ス部にハンドシエーク制御信号のタイミングを可
変設定するタイミング制御部が設けられているこ
とを特徴とする入出力ポート。
In an input/output port that transfers data from a transmitting side to a receiving side using handshake control, a timing control unit that variably sets the timing of a handshake control signal is provided in an interface unit with the transmitting side and/or the receiving side. An input/output port characterized by:
JP9119488U 1988-07-08 1988-07-08 Pending JPH0214153U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9119488U JPH0214153U (en) 1988-07-08 1988-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9119488U JPH0214153U (en) 1988-07-08 1988-07-08

Publications (1)

Publication Number Publication Date
JPH0214153U true JPH0214153U (en) 1990-01-29

Family

ID=31315682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9119488U Pending JPH0214153U (en) 1988-07-08 1988-07-08

Country Status (1)

Country Link
JP (1) JPH0214153U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54103980U (en) * 1977-12-28 1979-07-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54103980U (en) * 1977-12-28 1979-07-21

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