JPS63196969A - Timing circuit - Google Patents

Abstract

PURPOSE:To continuously execute at short time intervals a processing cycle until a processing request signal is released after a logic circuit has outputted the processing request signal, by providing a delay control circuit in parallel to a delaying circuit. CONSTITUTION:A delay control circuit 17 is constituted of an inverter 4 and a resistance 6 whose resistance value is smaller than that of a resistance 5 of a delaying circuit 5. In such a state, when a logic circuit 1 outputs a processing request signal S1 to a logic circuit 2 and the circuit 15 at a time t1, the output level of the circuit 15 goes to '1' at the time which is delayed by the time determined by a time constant. Subsequently, at a time t2, a level S2 of the signal S1 is inverted and a processing end signal S3 is outputted to the circuit 1 through a NAND gate 9. The circuit 1 releases the signal S1 at a time t3, and at a time t4 which has elapsed by the time T2 from the time t3, charge of a capacitor 7 is discharged through the resistance 6 of the circuit 17, and the level S2 of the circuit 15 is reset to '0'. Accordingly, when the signal S1 of the next cycle has appeared at a time t5, the signal S3 is outputted to the circuit 1 at a time t7, ad the processing cycle from the time t5 goes to normal, and can be executed continuously in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing circuit for providing appropriate timing for signal transmission between two logic circuits.

(Prior Art) FIG. 3 is a circuit diagram of a conventional example of this type of timing circuit, and FIG. 4 is a timing diagram of the circuit shown in FIG.

Time 1. When the logic circuit 1 outputs the processing request signal SI of logic level "0", the logic circuit 2 inputs the signal sI and performs logic processing. At the same time, the signal sI is input to a delay circuit 15 consisting of an inverter 3, a resistor 5, and a capacitor 7. And the time T determined by the time constant of the delay circuit 15
, how late is the time t? At this time, the logic level s4 on the upper side 3 of the capacitor 7 becomes "1". This signal s4 of logic level "1" and the signal whose logic level of processing request No. 48 SI is inverted by the inverter 10 and becomes logic "1" are input to the Nantes gate 9, and at time t2, the Nantes gate 9 is switched to the logic A processing end signal S5 of level "0" is output to the logic circuit 1. A logic circuit l inputs a processing end signal S at time t2.
releases the processing request signal S1 at time t3, and the logic level of the processing request signal SL becomes "1". This completes one processing cycle.

Next, a time T1 determined by the time constants of the capacitor 7 and the resistor 5 is required from the end of the processing cycle at time t3 until the output logic level S4 of the delay circuit 15 becomes "0". The time t when this time T elapses is also the same as the previous time t5, and the logic level of the processing request signal S of the next processing cycle is "
0" is output from the logic circuit 1. In this case, the previous processing cycle ends at time t3, the capacitor 7 of the delay circuit 15 is discharged, and the time t when the logic level S becomes "0" is also the same as the previous one. At time t5, the inverter IO inverts the logic level of the processing request signal SI to the logic level "1" at the Nant gate 9, and the signal whose level is "1'".
The output logic level S4 of the delay circuit 15 is input. As a result, the processing end signal S5 of the processing cycle starting from time t5 is sent to the logic circuit at time t5 without waiting for time t7 when the next processing cycle ends after time T has elapsed since time t5 when the next processing cycle started. 1 will be input.

Therefore, the timing circuit shown in FIG. 5 is a slightly improved version of the circuit shown in FIG. 3 described above. In this timing circuit, a diode 12 and a resistor 11 are connected in parallel with the resistor 5, so that the logic level at one end 14 of the capacitor becomes "0" earlier than before. Since the action of the resistor 11 limits the speed at which the logic level at one end 14 of the capacitor 7 reaches "θ", it is not possible to perform successive processing cycles at very short time intervals, similar to the circuit of FIG.

(Problems to be Solved by the Invention) The above-mentioned conventional timing circuit has the disadvantage that it cannot continuously execute the processing cycle from when the logic circuit outputs a processing request signal to when this signal is released at short time intervals. There is.

(Means for Solving the Problems) The timing circuit of the present invention provides a timing circuit that, after a processing cycle from when a logic circuit that outputs a processing request signal outputs the processing request signal to when the processing request signal is released, is completed. The logic circuit that receives the processing request signal receives the processing request signal when a preset time that is less than or equal to the minimum time from when the processing request signal is released to when the next processing request signal is output. The present invention includes a delay control circuit that returns the output logic level of a delay circuit that delays the processing request signal in accordance with the time from the time to the end of the logic processing to the logic level immediately before the processing end signal is output.

(Operation) Therefore, the processing cycle from when the logic circuit outputs the processing request signal to when the processing request signal is released can be executed continuously at short time intervals.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the timing circuit of the present invention, and FIG. 2 is a timing diagram of the circuit shown in FIG.

The delay control circuit 17 is configured to control the delay control circuit 17 when a preset time T2 has elapsed after the logic circuit 1 outputting the processing request signal SL has completed a processing cycle from outputting the processing request signal SL to canceling the processing request signal S1. , processing request signal S1
The processing end signal S3 is outputted from the output logic level S2 of the delay circuit 15, which has a time constant corresponding to the time T from when the logic circuit 2 receiving the processing request signal SI receives the processing request signal SI to when the logic circuit 2 finishes the logic processing. This circuit returns the logic level to the logic level just before the inverter 3 is activated.
The resistor 5 is connected in parallel to the series circuit of the inverter 3 and the resistor 5 of the delay circuit 15 consisting of the resistor 5 and the capacitor 7.

Note that the time T2 is set in advance to be less than or equal to the minimum time from the time the processing request signal SL is released until the next processing request signal SL is output.

The processing end signal output circuit 16 consists of an inverter 10 and a Nant gate 9.

Next, the operation of the timing circuit of this embodiment will be explained.

First, at time t, when the logic circuit 1 outputs the processing request signal SI of logic level "0", the logic circuit 2 receives the processing request signal S and performs logic processing. At the same time, the processing request signal S is input to a delay circuit 15 consisting of an inverter 3, a resistor 5, and a capacitor 7. and delay circuit 15
The output logic level S2 of the delay circuit 15 (the logic level at the upper end 8 of the capacitor 7) becomes "1" at time t2, which is delayed by a time T determined by the time constant of . At time t2, this logic level "1" and the inverter IO cause the processing request signal S,
The signal whose logic level is inverted and becomes logic level '1' is input to the Nantes gate 9, and the Nantes gate 9 outputs a processing end signal S3 of logic level '0' to the logic circuit!.At time t2. Logic circuit 1 that receives the processing end signal S3
releases the processing request signal S at time t3, and the logic level of the processing request signal S becomes '1'. At time t4, which is a time period T2 after time t3, the charge in the capacitor 7 is discharged through the resistor 6. The output logic level S2 of the delay circuit 15 returns to logic "0".

Therefore, when the processing request signal Sl of the next processing cycle appears at an early time t5 after time t4, the processing end signal S3 is output to the logic circuit 1 at time t7, which is after time T has elapsed from time t5, and at time t5. Processing cycles starting from will proceed normally.

(Effects of the Invention) As explained above, the present invention provides a method that allows the logic circuit that outputs the processing request signal to wait in advance for less than or equal to the minimum time from when the logic circuit that outputs the processing request signal releases the processing request signal until it outputs the next processing request signal. By providing a delay control circuit that returns the logic level of the delay circuit to the logic level immediately before the processing end signal was output when a set time elapses, the processing request signal is output after the logic circuit outputs the processing request signal. This has the advantage that the processing cycles up to release can be executed continuously at short time intervals.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the timing circuit of the present invention, FIG. 2 is a timing diagram of the circuit in FIG. 1, FIGS. 3 and 5 are circuit diagrams showing conventional timing circuits, and FIG. FIG. 4 is a timing diagram of the circuit of FIG. 1.2--Logic circuit, 3.10- Inverter, 4-- Open collector output inverter, 5.6-
...Resistor, 7.-Capacitor, 9.Nands gate, 15.-Delay circuit, 16--Processing end signal output circuit, +7-.Delay control circuit, S,-.Processing request signal, S2 ...Output logic level of delay circuit 15, S3-...
Processing end signal.

Claims (1)

[Scope of Claims] A delay circuit that delays a processing request signal in accordance with the time from when a second logic circuit receives a processing request signal from a first logic circuit until it finishes logic processing, and the delay circuit. In a timing circuit having a processing end signal output circuit that inputs an output signal of the circuit and a processing request signal output from a first logic circuit and outputs a processing end signal, the first logic circuit outputs a processing request signal. After the processing cycle from when the processing request signal is output to when the processing request signal is released is completed, a preset time less than or equal to the minimum time from when the processing request signal is released until the next processing request signal is output. A timing circuit comprising: a delay control circuit that returns the output logic level of the delay circuit to the logic level immediately before the processing end signal was outputted when time elapses.