JPS63197366A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63197366A JPS63197366A JP3014587A JP3014587A JPS63197366A JP S63197366 A JPS63197366 A JP S63197366A JP 3014587 A JP3014587 A JP 3014587A JP 3014587 A JP3014587 A JP 3014587A JP S63197366 A JPS63197366 A JP S63197366A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- margin
- contact portion
- metal wiring
- contact part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 6
- 230000005012 migration Effects 0.000 abstract description 5
- 238000013508 migration Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 44
- 230000015556 catabolic process Effects 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に静電気等によ
る高電圧に対する絶縁破壊強度を向上した半導体集積回
路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device with improved dielectric breakdown strength against high voltages caused by static electricity or the like.
従来、半導体集積回路装置では静電気等の高電圧に対す
る絶縁破壊強度を向上するために、特にこれらの過電圧
が印加される外部端子の近傍では拡散層や金属配線にレ
イアウト上の工夫がなされている。例えば第３図の様に
半導体基板２１に形成した外部端子としての金属配線２
２と保護抵抗としての拡散層２３とのコンタクト部２４
に拡散層端の余裕２３５１を設けている。またこれに近
接する金属配線２５と他の拡散層（例えばＶｃｃ電位）
２６とのコンタクト部２７を前記保護抵抗としての拡散
層２３から十分能される様に両者の間隔に十分な余裕を
設けている。Conventionally, in semiconductor integrated circuit devices, in order to improve dielectric breakdown strength against high voltages such as static electricity, layout improvements have been made to diffusion layers and metal wiring, especially in the vicinity of external terminals to which these overvoltages are applied. For example, as shown in FIG. 3, metal wiring 2 as an external terminal formed on a semiconductor substrate 21
A contact portion 24 between 2 and a diffusion layer 23 as a protective resistor.
A margin 2351 is provided at the end of the diffusion layer. Also, the metal wiring 25 and other diffusion layers (for example, Vcc potential) that are close to this
A sufficient margin is provided in the interval between the two so that the contact portion 27 with the protective resistor 26 can be sufficiently formed from the diffusion layer 23 serving as the protective resistor.
上述した従来のパターンレイアウトでは、前記し九箇所
における夫々の余裕は十分であるが、保護抵抗としての
拡散層２３に近接する金属配線２５と拡散層２６とのコ
ンタクト部２７における拡散層端の余裕については特に
考慮されることはなく、他の内部回路と同様に製造上の
最小余裕でパターン構成されている。In the conventional pattern layout described above, each of the above-mentioned nine locations has sufficient margin, but there is a margin at the end of the diffusion layer at the contact portion 27 between the metal wiring 25 and the diffusion layer 26, which are close to the diffusion layer 23 serving as a protective resistor. There is no particular consideration given to this, and the pattern is configured with the minimum manufacturing margin like other internal circuits.
ところで外部端子としての金属配線２２に静電気等によ
る高電圧が印加された場合、この金属配線２２に接続し
た拡散層２３とこれに近接する拡散層２６との間に電流
経路が構成されて多大な電流が流れることがある。する
と、この多大な電流とこれが原因とされる発熱によって
金属配線２２や２５において金属原子のマイグレーシラ
ン現象が引き起こされる。そして、この時上述の様に拡
散層２６と金属間９２５とのコンタクト部２７における
拡散層端の余裕が小さいと、この臂イグレーシ曹ン現象
は第４図に示す様に半導体基板２１とフィールド酸化膜
２８あるいは層間絶縁膜２９の界面を通して進行し、つ
いにはこの部分の絶縁を破壊して半導体基板２１と金属
間！ｓ２５を短絡させてしまうことになる。By the way, when a high voltage due to static electricity or the like is applied to the metal wiring 22 as an external terminal, a current path is formed between the diffusion layer 23 connected to the metal wiring 22 and the diffusion layer 26 adjacent thereto, and a large amount of current is generated. Current may flow. Then, due to this large amount of current and the heat generated thereby, a migration phenomenon of metal atoms is caused in the metal wirings 22 and 25. At this time, if the margin at the edge of the diffusion layer at the contact portion 27 between the diffusion layer 26 and the metal interlayer 925 is small as described above, this phenomenon of arm ignition occurs between the semiconductor substrate 21 and the field oxidation, as shown in FIG. It progresses through the interface of the film 28 or the interlayer insulating film 29, and finally breaks down the insulation in this part, causing a gap between the semiconductor substrate 21 and the metal! This will short-circuit s25.
このため、このコンタクト部２７における電圧強度が著
しく低下され、これによって半導体集積回路装置全体の
絶縁破壊強度が低され、その信頼性を低下させる原因と
なっている。For this reason, the voltage intensity at this contact portion 27 is significantly reduced, which reduces the dielectric breakdown strength of the entire semiconductor integrated circuit device, causing a reduction in its reliability.
上述した従来の外部端子としての金属配線と拡散層とを
接続するコンタクト部に近接する金属配線と拡散層とを
接続するコンタクト部においてはコンタクトと拡散層端
の余裕については何ら考慮がなされていなかったのに対
し、本発明は、そこのコンタクトと拡散層端の余裕を内
部回路等の他の箇所のコンタクト部の余裕より必らず大
きくしているという内容を有する。In the contact portion that connects the diffusion layer and the metal wire adjacent to the contact portion that connects the metal wire as the conventional external terminal and the diffusion layer, no consideration is given to the margin between the contact and the end of the diffusion layer. On the other hand, the present invention has the content that the margin between the contact and the end of the diffusion layer is always made larger than the margin of the contact portion at other locations such as the internal circuit.
本発明の半導体集積回路装置は、外部端子としての金属
配線と拡散層とを接続するコンタクト部に近接される金
属配線と拡散層とのコンタクト部における電圧強度を向
上し、半導体集積回路装置全体の電圧破壊強度の向上及
びその信頼性の向上を達成するものである。The semiconductor integrated circuit device of the present invention improves the voltage intensity at the contact portion between the metal wire and the diffusion layer that is close to the contact portion that connects the metal wire as an external terminal and the diffusion layer, and improves the voltage strength of the entire semiconductor integrated circuit device. This improves voltage breakdown strength and reliability.
本発明の半導体集積回路装置は、外部端子としての金属
配線と拡散層とを接続するコンタクト部に近接される金
属配線と拡散層とのコンタクト部における拡散層端の余
裕を少なくとも他のコンタクト部よりも大きく形成する
構成としている。In the semiconductor integrated circuit device of the present invention, the margin of the end of the diffusion layer in the contact portion between the metal wire and the diffusion layer that is brought close to the contact portion connecting the metal wire as an external terminal and the diffusion layer is at least larger than that of other contact portions. It is also configured to have a large shape.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示しておシ、シリコン等の
半導体基板１上には外部端子としての金属間＠２を設け
、これを半導体基板１の主面に形成した保護抵抗として
のＮｆｉ拡散層３にコンタクト部４で接続している。ま
た、この拡散層３に近接する位置にはＶＣＣ電位に接続
される金属配線５及びＮ型拡散層６を配設し、両者をコ
ンタクト部７において接続している。FIG. 1 shows an embodiment of the present invention, in which a metal intermetal @2 is provided as an external terminal on a semiconductor substrate 1 made of silicon, etc., and this is used as a protective resistor formed on the main surface of the semiconductor substrate 1. It is connected to the Nfi diffusion layer 3 through a contact portion 4. Further, a metal wiring 5 connected to the VCC potential and an N-type diffusion layer 6 are provided in a position close to this diffusion layer 3, and both are connected at a contact portion 7.
そして、前記コンタクト部４ではこれまでと同様に拡散
層３の端部の余裕３ａを十分大きなものに設定するとと
もに、前記コンタクト部７においても拡散層６の端部の
余裕６ａを可及的に大きく設定している。特に、この拡
散層６の余裕６ａは、内部回路等の他の箇所におけるコ
ンタクト部よシ４十分大きな寸法に設定している。In the contact part 4, the margin 3a at the end of the diffusion layer 3 is set to be sufficiently large as before, and in the contact part 7, the margin 6a at the end of the diffusion layer 6 is set as much as possible. It is set large. In particular, the margin 6a of the diffusion layer 6 is set to be sufficiently larger than the contact portion 4 at other locations such as the internal circuit.
したがって、この構成によれば外部端子としての金属配
線２に静電気等による高電圧が印加された場合に、上述
したように拡散層３と６との間に電流経路が形成され、
この電流及びこれに伴う発熱が原因となって各金属配線
２と５にマイグレーシ曹ン現象が引き起こされるが、コ
ンタクト部７には拡散層６の大きな余裕６ａを設けてい
るために、第４図に示したような界面を通してのマイグ
レーシ冒ンの進行が生ずることはなく半導体基板１と金
属配線５等との短絡を防止してその絶縁破壊の強度を向
上できる。Therefore, according to this configuration, when a high voltage due to static electricity or the like is applied to the metal wiring 2 as an external terminal, a current path is formed between the diffusion layers 3 and 6 as described above.
This current and the accompanying heat generation cause a migration phenomenon in the metal wirings 2 and 5, but since the contact portion 7 is provided with a large margin 6a of the diffusion layer 6, as shown in FIG. The progress of migration through the interface as shown in FIG. 1 does not occur, and short circuits between the semiconductor substrate 1 and the metal wiring 5, etc. can be prevented, and the strength of dielectric breakdown can be improved.
因に、本発明者の測定によれば、余裕が０．５μｍでは
破壊電圧が２００Ｖであったものが、余裕を１．５μｍ
にすることによって破壊電圧を４００Ｖに改善できた。Incidentally, according to the inventor's measurements, when the margin was 0.5 μm, the breakdown voltage was 200 V, but when the margin was 1.5 μm, the breakdown voltage was 200 V.
By doing so, the breakdown voltage could be improved to 400V.
なお、第１図では拡散層６０幅寸法を一様に増大してコ
ンタクト部７における余裕６ａを大きくしているが、拡
散層３において設けた余裕と同様に、拡散層６のコンタ
クト部７における幅のみを大きくした構成にしても十分
本発明の目的を達成することができる。Note that in FIG. 1, the width dimension of the diffusion layer 60 is uniformly increased to increase the margin 6a in the contact portion 7; however, similar to the margin provided in the diffusion layer 3, the width dimension of the diffusion layer 6 is Even if only the width is increased, the object of the present invention can be sufficiently achieved.
次に本発明の第２の実施例を図面を参照して説明する。Next, a second embodiment of the present invention will be described with reference to the drawings.
図２に第２の実施例を示す。シリコン等の半導体基板１
１上には、外部端子としての金属配線１２を設け、これ
を半導体基板１１の主面に形成した保護抵抗としてのＮ
型拡散層１３にコンタクト部１４で接続している。また
この入力コンタクト部１４に近接して保護抵抗としての
Ｎ型拡散層の他端側のコンタクト部１７がある。コンタ
クト部１７の拡散層１３との余裕１６ａは、内部回路等
の他の箇所におけるコンタクト部より十分大きな寸法に
設定しである。この構成の場合の静電気等による高電圧
が印加された時の電流経路は、拡散層抵抗１３を介する
ものと、コンタクト部１４→半導体基板１１→コンタク
ト部１７という２つの経路が考えられるが、この時拡散
層抵抗１３の抵抗値が大きければ大きいほど、；ンタク
ト部１４→半導体基板→コンタクト部１７という経路を
流れる電流は大きくなる。通常保護抵抗としての拡散抵
抗の抵抗値ＩＫΩ程度に設廻嘔れるが本発明者に測定に
よればＩＫΩ程度の値では、コンタクト部１７の破壊が
コンタクト部１７の余裕１６ｍによって左右され、第１
の実施例と同じ結果となる。FIG. 2 shows a second embodiment. Semiconductor substrate 1 such as silicon
A metal wiring 12 as an external terminal is provided on the semiconductor substrate 11, and a metal wiring 12 as a protective resistor is formed on the main surface of the semiconductor substrate 11.
It is connected to the type diffusion layer 13 through a contact portion 14 . Further, close to this input contact portion 14, there is a contact portion 17 on the other end side of the N-type diffusion layer as a protection resistor. The margin 16a between the contact portion 17 and the diffusion layer 13 is set to be sufficiently larger than the contact portion at other locations such as the internal circuit. In this configuration, there are two possible current paths when a high voltage is applied due to static electricity or the like: one via the diffusion layer resistor 13, and the other via the contact portion 14→semiconductor substrate 11→contact portion 17. The larger the resistance value of the diffusion layer resistor 13, the larger the current flowing through the path: contact portion 14→semiconductor substrate→contact portion 17. Normally, the resistance value of the diffused resistor as a protective resistor is set to about IKΩ, but according to measurements by the present inventor, when the resistance value is about IKΩ, the breakdown of the contact portion 17 is affected by the margin of 16 m of the contact portion 17, and the first
The result is the same as in the example.
また前記２つの実施例ではＮｆｉ拡紋層で例示したがＰ
型拡散層でも同じであシ、ま九近接しているコンタクト
部がＧＮＤやその他の電位でも同様に適用できる。In addition, in the above two embodiments, the Nfi spreading layer was used as an example, but P
The same applies to the type diffusion layer, and the same applies even if the adjacent contact portion is at GND or other potential.
以上説明したように本発明は、外部端子としての金属配
線と拡散層とを接続するコンタクト部に近接される金属
配線と拡散層とのコンタクト部における拡散層端余裕を
少なくとも他のコンタクト部よシ大きく形成しているの
で、外部端子としての金属配線と拡散層とを接続するコ
ンタクト部から通流される電流によって起こるマイグレ
ーシ璽ン現象によるコンタクト部の絶縁破壊を有効に防
止でき、これによシ半導体集積回路装置全体の高電圧に
対する破壊強度を向上しかつその信頼性を向上できる。As explained above, the present invention provides at least a diffusion layer edge margin at a contact portion between a metal wire and a diffusion layer that are close to a contact portion connecting a metal wire as an external terminal and a diffusion layer. Because it is formed large, it is possible to effectively prevent dielectric breakdown of the contact part due to the migration phenomenon caused by the current flowing from the contact part that connects the metal wiring as an external terminal and the diffusion layer. The breakdown strength of the entire integrated circuit device against high voltage can be improved and its reliability can be improved.
第１図は本発明の第１の実施例の要部の平面図、第２図
は本発明の第２実施例の要部の平面図、第３図は従来例
の要部の平面図、第４図は第３図のＡＡ線に沿う断面図
である。
１．１１．２１・・・・・・半導体基板、２，１２，２
２・・・・・・外部端子としての金属配線、３，６，１
３，２３゜２６・・・・・・Ｎ型拡散層、３ａ、１３ａ
、２３ａ、６ａ。
１６ ａ ＝−−−・余裕、４，７，１４，１７，２４
．２７−・−・−コンタクト部、５．２５・・・・・・
Ｖｃｃ電位の金属配線、２８・・・・・・フィールド酸
化膜、２９・・・・・・層間絶縁膜。
代理人 弁理士 内 原 晋 ゛ｌ≧、（２、。
＼５−゛FIG. 1 is a plan view of the main parts of the first embodiment of the present invention, FIG. 2 is a plan view of the main parts of the second embodiment of the invention, and FIG. 3 is a plan view of the main parts of the conventional example. FIG. 4 is a sectional view taken along line AA in FIG. 3. 1.11.21... Semiconductor substrate, 2, 12, 2
2...Metal wiring as external terminal, 3, 6, 1
3,23゜26...N-type diffusion layer, 3a, 13a
, 23a, 6a. 16 a =---・Margin, 4, 7, 14, 17, 24
．． 27--Contact part, 5.25...
Vcc potential metal wiring, 28... field oxide film, 29... interlayer insulating film. Agent Patent Attorney Susumu Uchihara ゛l≧, (2,. \5-゛
Claims (2)
散層を接続するコンタクト部と、このコンタクト部に近
接された金属配線と拡散層を接続する第１のコンタクト
部とを備える半導体集積回路装置において、前記外部端
子としての金属配線と拡散層を接続するコンタクト部に
近接される前記金属配線及び拡散層の第２のコンタクト
部における拡散層端の余裕を少なくとも他のコンタクト
部よりも大きく形成したことを特徴とする半導体集積回
路装置。(1) A semiconductor integrated circuit comprising, on a semiconductor substrate, a contact portion that connects a metal wiring serving as an external terminal and a diffusion layer, and a first contact portion that connects the metal wiring and the diffusion layer in proximity to the contact portion. In the device, a second contact portion of the metal wiring and diffusion layer that is close to a contact portion connecting the metal wiring as the external terminal and the diffusion layer is formed with a margin larger than at least other contact portions. A semiconductor integrated circuit device characterized by:
を半導体集積回路の製造上の最小余裕よりも大きくして
なる特許請求の範囲第１項記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the margin at the end of the diffusion layer in the second contact portion is larger than the minimum margin for manufacturing the semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3014587A JPS63197366A (en) | 1987-02-10 | 1987-02-10 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3014587A JPS63197366A (en) | 1987-02-10 | 1987-02-10 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63197366A true JPS63197366A (en) | 1988-08-16 |
Family
ID=12295595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3014587A Pending JPS63197366A (en) | 1987-02-10 | 1987-02-10 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63197366A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS513182A (en) * | 1974-06-25 | 1976-01-12 | Nippon Electric Co | |
| JPS56124266A (en) * | 1980-03-03 | 1981-09-29 | Mitsubishi Electric Corp | Semiconductor device |
| JPS62165362A (en) * | 1986-01-17 | 1987-07-21 | Nec Corp | Semiconductor integrated circuit device |
-
1987
- 1987-02-10 JP JP3014587A patent/JPS63197366A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS513182A (en) * | 1974-06-25 | 1976-01-12 | Nippon Electric Co | |
| JPS56124266A (en) * | 1980-03-03 | 1981-09-29 | Mitsubishi Electric Corp | Semiconductor device |
| JPS62165362A (en) * | 1986-01-17 | 1987-07-21 | Nec Corp | Semiconductor integrated circuit device |
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