JPS63200938U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Bit pattern comparison circuit, 1a, 1b,
1c...Input terminal, 1d, 2b, 3b, 4c...
Output terminal, 2...Error bit counting circuit, 3...
Total bit counting circuit, 4... Memory circuit, 4a
, 4b...Input terminal, 5...Data display circuit, 6
...Demodulated data, 7...Bit pattern, 8...
Demodulation clock, 9...Pulse, 10...Pulse count value, 11...Clock count value, 12...Bit error rate data.

Claims (1)

[Scope of utility model registration request] In a bit error rate measurement circuit that measures the bit error rate of demodulated data demodulated by a data demodulator in a data transmission system in accordance with a demodulation clock, the demodulation clock of the demodulation device is input to a clock input terminal, and the A bit pattern comparison circuit that compares the demodulated data and a preset bit pattern bit by bit and outputs a pulse each time it recognizes a bit that does not match, and a count value that counts the pulses supplied from the bit pattern comparison circuit. an error bit counting circuit that sequentially outputs the bit count value as a bit count value; a total bit count circuit that counts the clock input to the clock input terminal of the bit pattern comparison circuit and sequentially outputs the count value as a clock count value; A memory circuit that uses a combination of a bit count value and the clock count value as address data and successively outputs bit error rate data stored in advance in a memory location determined by this address data, and a bit error rate read out from this memory circuit. A bit error rate measuring circuit comprising: a data display circuit that sequentially displays data.