JPS63201345U - - Google Patents
Info
- Publication number
- JPS63201345U JPS63201345U JP1987093515U JP9351587U JPS63201345U JP S63201345 U JPS63201345 U JP S63201345U JP 1987093515 U JP1987093515 U JP 1987093515U JP 9351587 U JP9351587 U JP 9351587U JP S63201345 U JPS63201345 U JP S63201345U
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor device
- semiconductor element
- island
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す平面図、第２図
及び第３図は従来例を示す平面図である。 １は半導体素子、３はアイランド、４，４′，
５は外部リード、６は導線。
及び第３図は従来例を示す平面図である。 １は半導体素子、３はアイランド、４，４′，
５は外部リード、６は導線。
Claims (1)
- アイランド上に半導体素子が搭載され、前記半
導体素子上の２領域間をボンデイングし、且つ、
前記アイランド近傍に延在されたリードとボンデ
イングされる前記２領域間を接続する半導体装置
において、前記２領域間を接続するボンデイング
方向に対して実質的に逆方向に前記半導体素子の
他の領域と他のリードとをボンデイングして成る
半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987093515U JPS63201345U (ja) | 1987-06-18 | 1987-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987093515U JPS63201345U (ja) | 1987-06-18 | 1987-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63201345U true JPS63201345U (ja) | 1988-12-26 |
Family
ID=30956156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987093515U Pending JPS63201345U (ja) | 1987-06-18 | 1987-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63201345U (ja) |
-
1987
- 1987-06-18 JP JP1987093515U patent/JPS63201345U/ja active Pending