JPS63201729A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To collect a bit of interrupting information at the time of generation of an interruption factor, even when an interruption processing is inhibited, by providing an interrupting information storing means for storing the interrupting information, and an interrupting information storage control means for storing the interrupting information in the interrupting information storing means in response to the generation of the interruption factor. CONSTITUTION:The titled circuit is provided with an interrupting information store control part 1 for executing the detection of an interruption factor, a store and the storage control of interrupting information, an interrupting information storing part 2 for storing the interrupting information of a CC (central processing unit) status, etc., a sequencer 3 for controlling an execution of a micro-instruction, and a micro- memory part (mu-memory part) 4 for storing a microprogram. Also, an executing circuit 5 for decoding and executing the micro-instruction is contained, and an interruption control circuit is constituted of the interrupting information storage control part 1 and the interrupting information storing part 2, and a program executing part is constituted of the sequencer 3 and the micro-memory part 4. In such a way, even when the interruption factor is generated in the case of inhibiting an interruption processing, the interruption information can be stored without exerting an influence on the processing of the program executing part.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an interrupt control circuit for an information processing device.

[Traditional technique j nete]

Generally, in an information processing device that has an interrupt function, a program that performs interrupt processing is installed in the program execution section in addition to a program that performs normal processing, and the interrupt cause is transmitted from the interrupt control circuit. By adding
It is configured to suspend normal processing in the program execution section, execute an interrupt processing program corresponding to the interrupt factor, and collect the status of each section of the device.

By the way, if we assume that interrupt processing is executed whenever an interrupt factor occurs, normal processing will be interrupted every time an interrupt factor occurs, so if you are in the middle of a process that would be troublesome if it were interrupted, In some cases, the interrupt control circuit is provided with a control means that does not notify the program execution unit even if an interrupt factor occurs.

Conventionally, in such an interrupt control circuit, an interrupt factor that occurs while interrupt processing is prohibited by the control means is stored in an interrupt factor storage means, and when the prohibition of interrupt processing is canceled. The program execution unit is notified when the process is completed.

[Problem that the invention seeks to solve]

However, according to the conventional interrupt control circuit as described above,
For example, as shown in Figure 4, if an interrupt factor such as a device error occurs while interrupt processing is prohibited, the interrupt factor will be memorized, but at that point the state of each part of the device etc. Interrupt information is not stored, and the interrupt information is only stored when the program execution unit that is later allowed to handle interrupts handles the interrupt. There was a problem in that it was not possible to collect originally required interrupt information such as the status of each part.

Note that if interrupt processing is enabled, the interrupt processing will start immediately when an interrupt factor occurs, and it will be possible to collect information at the desired point in time, but if you do this, as mentioned above,
Normal processing in the program execution section will be interrupted.

The present invention solves the above-mentioned problems, and its purpose is to eliminate interrupt processing without affecting normal processing in the program execution section, that is, even when interrupt processing is prohibited. The object is to enable collection of interrupt information at the time when a factor occurs.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention includes an interrupt factor storage means for storing a plurality of interrupt factors, and a program execution unit that executes interrupt processing corresponding to the interrupt factors stored in the interrupt factor storage means. An interrupt control circuit comprising: a control means for controlling whether or not to cause an interrupt to be performed; and an interrupt information storage means for storing interrupt information; The interrupt information storage control means stores interrupt information in the means.

[For production]

If an interrupt factor occurs while interrupt processing is disabled,
The interrupt information is stored in the interrupt information storage means by an interrupt information storage control means provided separately from the program execution section. Therefore, even when interrupt processing is prohibited, it is possible to store interrupt information when an interrupt factor occurs without affecting the normal processing of the program execution section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes an interrupt information storage control unit 1 that detects and stores interrupt factors, and controls the storage of interrupt information, and a CC' (solid processing unit) status indicator. an interrupt information storage section 2 that stores interrupt information, a sequencer 3 that controls the execution of microinstructions, and a micromemory section (μm memory section) 4 that stores microprograms.
It includes an execution circuit 5 that decodes and executes microinstructions, and an interrupt control circuit is configured by an interrupt information storage control section I and an interrupt information storage section 2, and a sequencer 3, a micromemory section 4, and an execution circuit 5. The circuit 5 constitutes a program execution section.

FIG. 2 is a block diagram showing an example of the configuration of each part shown in FIG. 1.

The interrupt information storage control unit 1 stores the old interrupt factor register 101
, new interrupt factor register 102, and EX-OR game 0
3, an inhibit gate 104, an oldest bit detection circuit 105, and a gate circuit 106, and the interrupt information storage unit 2 includes an interrupt information memory address register 201 and a register for temporarily storing interrupt information. It is composed of a hasher circuit 202, an interrupt information memory 203 that stores interrupt information, and an interrupt information memory control circuit 204, and the sequencer 3
is an interrupt address generation circuit 301 that generates an interrupt address.
And normal processing.

The micromemory unit 4 includes a selection circuit 302 that selects an address for interrupt processing, and a microprogram memory address register 401 and a microprogram memory 402 that stores a microprogram. The execution circuit 5 also includes a microinstruction decoder 50.
Contains 1.

The old interrupt factor register 101 and the new interrupt factor register 102 in the interrupt information storage control unit 1 have the same bit configuration, and each bit corresponds to a different interrupt factor.
The bits on the right side correspond to higher level interrupt factors.

Also, each bit of the new interrupt factor register 102 is set to “1” once.
'' is set, its contents are retained until it is reset.Furthermore, the gate circuit 106 provided between the old interrupt cause register 101 and the new interrupt cause register 102 The signal at the bit position specified by the control signal from the oldest bit detection circuit 105 of the output signal of the interrupt factor register 102 is sent to the old interrupt factor register 1.
It is added to the corresponding bit of 01.

For example, N of the output signals of the new interrupt factor register 102
If the bit is specified, that signal is added to the ON bit of the old interrupt factor register 101.

In FIG. 2, when the first interrupt factor occurs after the old interrupt factor register 101 and the new interrupt factor register 102 are reset, the following processing is performed. When a single interrupt factor or a plurality of interrupt factors occur simultaneously when an interrupt factor occurs for the first time, "1" is set in the bit corresponding to the above-mentioned interrupt factor in the new interrupt factor register 102. Then, the exclusive OR of the output signal of the new interrupt factor register 102 and the output signal of the old interrupt factor register 101 is EX-O.
It is taken at R gate 103. In this case, the output signal of the old interrupt factor register 101 is all bits "θ", so E
The output signal of the X-OR gate 103 is the same as the output signal of the new interrupt cause register 102. And EX-
The output signal of the OR gate 103 is sent to the rightmost bit detection circuit 10.
5, and the rightmost bit detection circuit 105 is added to EX-OR
The bit position of the rightmost bit of the bits that are “1” in the output signal of the gate 103 is detected, and the detection result is set in the interrupt information memory address register 201 and is also sent to the interrupt information memory control circuit 204. Add writing instructions. That is, the rightmost bit detection circuit 105 detects the highest level of the interrupt factors that occurred when the first interrupt factor occurred, and stores the value corresponding to the detected interrupt factor in the interrupt information memory address register 201. It will be set.

In addition, the buffer circuit 202 stores the interrupt information at the same time as the above-mentioned interrupt factor occurs, regardless of whether interrupt processing is permitted or not, and the interrupt information memory control circuit 204 When a write instruction is applied from the rightmost bit detection circuit 105, the interrupt information stored in the buffer circuit 202 is stored in the area corresponding to the value set in the interrupt information memory address register 201 of the interrupt information memory 203. Write at once or in multiple parts. Here, the value stored in the interrupt information memory address register 201 is the value corresponding to the highest level interrupt factor among the interrupt factors that occurred when the first interrupt factor occurred. The interrupt information stored in is written to the area of the interrupt information memory 203 corresponding to the highest level interrupt factor among the interrupt factors that occurred simultaneously.

Further, after the rightmost bit detection circuit 105 applies a write instruction to the interrupt information memory control circuit 204, the gate circuit 106
A control signal is added to the output signal of the new interrupt factor register 102 (the same bit as the rightmost bit of the bits that are 1" in the output signal of the EX-OR gate 103) The signal is sent to the corresponding bit of the old interrupt factor register 101.If there is only one interrupt factor □ that occurred when the first interrupt factor occurred, by performing the above processing, the old interrupt factor register The contents of 101 and the contents of new interrupt factor register 102 become the same, and EX-
Since the output signals of the OR gate 103 are all “0”,
The storage process of interrupt information when the first interrupt factor occurs is completed, but if there are multiple interrupt factors that occurred when the first interrupt factor occurred, the contents of the old interrupt factor register 101 and the new interrupt The contents of the cause register 102 are not the same, and EX
Since the output signals of the -OR gate 103 do not all become "0", the same processing as described above is performed. in this case,
The rightmost bit of the bits that are "1" in the output signal of the EX-OR gate 103 corresponds to the second highest level interrupt factor among the interrupt factors that occurred when the first interrupt occurred. Therefore, the interrupt information stored in the buffer circuit 202 is stored in the area of the interrupt information memory 203 corresponding to the interrupt factor with the second highest level.

Then, when the second interrupt factor occurs after the above processing for the first interrupt factor that occurred after resetting the old interrupt factor register 101 and the new interrupt factor register 102 is completed, the next interrupt factor occurs. Such processing is performed.

As mentioned above, each bit of the new interrupt factor register 102 retains its contents until it is set to "1", so when the second interrupt factor occurs, a new interrupt The bits in the interrupt factor register 102 corresponding to the first and second interrupt factors are “1”.
becomes. Also, at this time, only the bit in the old interrupt factor register 101 corresponding to the first interrupt factor is set to "1".

Therefore, if the interrupt factor that occurred when the second interrupt factor occurred includes an interrupt factor other than the interrupt factor that occurred when the first interrupt factor occurred, the output signal of the EX-OR gate 103 Among them, when the second interrupt factor occurs, only the bit corresponding to the newly generated interrupt factor becomes "1" and is added to the tension bit detection circuit 105, and the same processing as described above is performed, and the interrupt The interrupt information stored in the buffer circuit 202 is written to a predetermined area of the information memory 203 (an area corresponding to the interrupt factor with the highest level among the interrupt factors that occurred when the second interrupt factor occurred). be included. On the other hand, if the interrupt factors that occurred when the second interrupt factor occurred are all included in the interrupt factors that occurred when the first interrupt factor occurred, all the output signals of the EX-OR gate 103 are bit"
0'', the tension bit detection circuit 105 does not perform any processing. In other words, the interrupt factor that occurred when the -th interrupt factor occurred and the interrupt factor that occurred when the second interrupt factor occurred are of the same type. In this case, the process of writing the interrupt information to the interrupt information memory 203 is performed only when the -th interrupt factor occurs, and the interrupt information is overwritten when the second interrupt factor occurs. The interrupt information written when the -th interrupt factor occurs is saved.
This system focuses on the fact that interrupt information at the time when an interrupt factor first occurs is useful for information analysis in interrupt processing, and the amount of memory used can be reduced.

Similar processing is performed for the third and subsequent occurrences of interrupt factors. The storage of the interrupt information that has been explained so far is
Regardless of whether interrupt processing is disabled or enabled, it is executed by the hardware and does not affect the flow of the microprogram.

Furthermore, if an interrupt factor occurs when interrupt processing is enabled, that is, when the interrupt processing disable signal applied to the inhibit gate 104 is set to "0", the flow of the microprogram will change at that point. change. That is, the address corresponding to the highest level interrupt factor among the generated interrupt factors is generated by the interrupt address generation circuit 301 that receives the output signal of the new interrupt factor register 102, and this address is used as the inhibit address.
The interrupt address generation circuit 3 uses the output signal of the node gate 104.
It is selected by the selection circuit 302 that switches to the 01 side, and is set in the microprogram memory address register 401.

Therefore, the microinstruction for interrupt processing is read from the microprogram memo 1J402, decoded by the microinstruction decoder 501, and the interrupt processing is executed.

On the other hand, the state where interrupt processing is prohibited, that is,
If an interrupt factor occurs while the interrupt processing prohibition signal applied to the inhibit gate 104 is on the verge of being turned off, the selection circuit 302 will not switch to the interrupt address generation circuit 301 side, so the interrupt processing will not be processed at that point. is not executed, therefore, the flow of the microprogram remains the same, and only the interrupt cause and interrupt information are stored.Then, when interrupt processing is permitted, the selection circuit 302 is switched and a new interrupt is selected. The addresses stored in the interrupt factor register 102 are assigned to the interrupt address generation circuit 3 in order of the interrupt factors with the highest level.
01, and interrupt processing corresponding to each interrupt factor is executed sequentially from the highest level. At this time, the interrupt information stored in the interrupt information memo 1J203 at the time when the interrupt factor occurs is used.

Note that the old interrupt cause disk 101. New interrupt factor register 1
The reset of 02 is performed, for example, after interrupt processing is enabled and all interrupt processing corresponding to the interrupt factors stored in the new interrupt factor register 102 is executed.

Figure 3 shows the processing in the present invention when an interrupt factor occurs when interrupt processing is disabled. This shows that the embedded information can be stored immediately in parallel with the normal processing by the microprogram.

Incidentally, in the embodiment described above, the interrupt information memory lJ'2
03 has an area corresponding to each interrupt factor, but
Of course, registers corresponding to each interrupt factor may be provided.

〔Effect of the invention〕

As explained above, in the present invention, when an interrupt factor occurs, an interrupt information storage unit such as the interrupt information memory 203 is configured to store an interrupt that is independent of a program execution unit such as the interrupt information storage control unit 1. Since the information storage control means stores interrupt information indicating the status of each part of the device at that time, even if an interrupt factor occurs while interrupt processing is prohibited, the program execution unit It is possible to store interrupt information at the time when an interrupt factor occurs without affecting the processing of the interrupt factor, and when the interrupt factor occurs later in interrupt processing when interrupt processing is enabled. This has the advantage of being able to use interrupt information that is accurate at the time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing in detail the configuration of each part shown in FIG. 1, FIG. 3 is a diagram showing processing contents according to the invention, and FIG. The figure is a diagram showing the processing contents of a conventional example. In the figure, 1... Interrupt information storage control unit, 2... Interrupt information storage unit, 3... Sequencer, 4... Micro memory unit, 5... Execution circuit, 101...・Old interrupt factor register, 102...New interrupt factor register, 103・
...EX-OR gate, 104...Inhibitor gate, 105...Paper bit detection circuit, 106...Gate circuit, 201...Interrupt information memory address register, 202...Buffer circuit , 203... Interrupt information memory, 204... Interrupt information memory control circuit, 301
...Interrupt address generation circuit, 302...Selection circuit,
401... Micro program memory address register, 402... Micro program memory, 501...
...Microinstruction decoder.

Claims (1)

[Scope of Claims] Interrupt factor storage means for storing a plurality of interrupt factors, and a program execution unit that determines whether or not to perform interrupt processing corresponding to the interrupt factors stored in the interrupt factor storage means. An interrupt control circuit comprising: a control means for controlling an interrupt; an interrupt information storage means for storing interrupt information; and an interrupt information storage means for storing interrupt information in the interrupt information storage means in response to occurrence of an interrupt factor. 1. An interrupt control circuit comprising: interrupt information storage control means.