JPS63201734A - Data processor testing system - Google Patents

Abstract

PURPOSE:To execute an error analysis without an assemble list of a test program and specification, by displaying a test object instruction as a part of an error message, when an error is detected by an instruction test of a data processor. CONSTITUTION:The titled system is provided with a registering means 1 registering a store address of the test object instruction, an environment setting means 2 setting an operation environment before executing the test object instruction, and an executing means 3 executing the test object instruction. Also, this system contains a checking means 4 checking presence of an error by comparing a result of execution of the test object instruction which is executed by the executing means 3 with an expected value, and a display means 5 displaying the test object instruction, based on an address registered by the registering means 1 as a part of an error message, when the error is detected by the checking means 4. in such a way, when an error is detected by an instruction test of a data processor, the test object instruction is displayed as a part of the error message. Accordingly, an error analysis can be executed without the assemble list of the test program and specification.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing method for a data processing device that sequentially executes instructions stored in a memory.

[Conventional technology]

Conventionally, in this type of data processing device testing method, when an execution result error of the instruction to be tested is detected, the result value of the data to be checked after execution of the instruction to be tested is displayed, but the instruction to be tested is not displayed. Ta.

[Problem that the invention seeks to solve]

In the conventional method described above, the instruction to be tested is not displayed when an error is detected as a result of executing the instruction to be tested.
The drawback is that it is necessary to look at the test program's assembly list and specifications for error analysis, and it takes a lot of time to detect the fault location.

[Means for solving problems]

The data processing device testing method of the present invention includes a registration means for registering a storage address of an instruction under test, an environment setting means for setting an operating environment before execution of the instruction under test, and an execution means for executing the instruction under test. , a checking means for checking the presence or absence of an error by comparing the execution result of the instruction to be tested executed by the execution means with an expected value, and registering the above as part of an error message when an error is detected by the checking means. It includes a display means for displaying the instruction to be tested based on the address registered by the means.

[For production]

In this way, by displaying the instruction to be tested as part of the error message when an error is detected in an instruction test of a data processing device, error analysis becomes possible without the test program assembly list or specifications. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, this embodiment includes a registration means 1, an environment setting means 2, an execution means 3, a checking means 4, a display means 5,
It consists of a test data block 6 and a console 7.

Referring to FIG. 2, the registration means 1 is comprised of clear 1a, check number registration 1b, check item registration 1C1 command address registration 1d. Referring to the third figure, the environment setting means 2 is comprised of a register check information registration 2a and a data check information registration 2b. Referring to FIG. 4, the execution means 3 consists of an instruction execution 3a. Referring to FIG. 5, the checking means 4 includes a register result value registration 4a, a register check 4b, a register error flag setting 4c, a data check 4d, and a data error flag setting 4e. Referring to FIG. 6, the display means 5 includes an error check 5a, an error message header output 5b, and a register error check 5.
C, register error information output 5d, data error check 5e, and data error information output 5f. Referring to FIG. 7, the test data block 6 includes an error flag 6a, a check number 6b, a check item address 6C, an instruction address 6d, and a register initial value address 6e.
, register result value address 6f, register expected value address 69, register mask value address 6h, data length 61
, data result value address 6j, data expected value address 6
k, and data mask value address 61.

Next, the operation of this embodiment will be explained with reference to the drawings.

First, clear the error flag 6au in the test data block 6 by clearing 1a of [registration means], register the 2-digit decimal check number 6b% for identifying test items with check number registration 1b, and register it in the check item address 6C. Then, in instruction address registration 1d, the address of the test target instruction indicated by instruction execution 3a is registered as instruction address 6d.

Next, register check information registration 2a of environment setting means 2
The address of the register expected value storage area prepared in advance to be checked in the register check 4b is set as the register expected value address 69, and the address of the register mask value prepared in advance to be checked in the register check 4b is set as the register mask value address. 6h, register the register value immediately before instruction execution 3a in the area of register initial value address 6e, set the number of bytes of data to be compared in data check 4d to data length 61 in data check information registration 2b, and set the data length 61 of the instruction execution 3a. The address of the data updated by the test target instruction shown in FIG. The address of a data mask value prepared in advance for this purpose is registered in the data mask value address 61.

Next, the instruction execution 3a of the execution means 3 executes the instruction to be tested.

Next, register result value registration 4a of checking means 4 registers the register value immediately after instruction execution 3a in the area indicated by register result value address 6f, and registers the register result value and register expected value in the area indicated by register expected value address 69. After taking a logical product with the register mask value of the area indicated by the register mask value address 6h, they are compared. If they are equal, the process moves to data check 4d, and if they are not equal, the error flag 6a is set by register error 7 flag setting 4C. After setting the register error flag bit to 1, the process moves to data check 4d. In the data check 4d, the data result value in the area indicated by the data result value address 6j and the data expected value in the area indicated by the data expected value address 6k are ANDed with the data mask value in the area indicated by the data mask value address 61. After that, they are compared, and if they are equal, the process goes to the display means 5. If they are not equal, the data error flag bit of the error flag 6a is set to 1 in the data error flag setting 4e, and then the process goes to the display means 5.

Next, the error flag 6a'lr is checked in the error check 5a of the display means 5, and if all bits are zero, the process is terminated, and if any bit is not zero, the check number indicated by the check number 6b is output in the error message header output 5b. , a message indicating the test summary indicated by the check item address 6C, and the test target instruction indicated by the instruction address 6d are displayed on the console 7, and the register initial value of the area indicated by the register initial value address 6e is displayed in the register error check 5C. displaying on the console 7 the register result value in the area indicated by the register result value address 6f, the register expected value in the area indicated by the register expected value address 6f, and the register mask value in the area indicated by the register mask value address 6h;
The data error check 5e checks the data error flag bit of the error flag 6a, and if it is zero, the process ends, and if it is not zero, the data error information output 5f displays the data result value indicated by the data result value address 6j and the data expected value. The expected data value indicated by address 6k and the data mask value indicated by data mask value address 61 are set to data length 6.
Only the number of bytes indicated by 1 is displayed on the console 7.

Through the above processing, the instruction to be tested is automatically displayed as part of the error message when an error is detected.

〔Effect of the invention〕

As explained above, the present invention displays the instruction to be tested as part of an error message when an error is detected in an instruction test of a data processing device, thereby eliminating the need for an assembly list or specifications of a test program. This has the effect of making error analysis possible.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the data processing bag M test method of the present invention, FIG. 2 is a flowchart of the registration means 1, FIG. 3 is a flowchart of the environment setting means 2, and FIG. 4 is a flowchart of the execution means 3. Flow chart, FIG. 5 is a flow chart of the checking means 4, FIG. 6 is a flow chart of the display means 5,
FIG. 7 is a diagram showing the format of the test data block 6. 1...Registration means, 2...Environment setting means, 3...Execution means, 4...Checking means, 5...Display means , 6... Test data block 7... Console. I't ID Ol)? +
N No. 00 Fig. 7

Claims (1)

[Scope of Claims] In a data processing device that sequentially executes instructions stored in a memory, there is provided a registration means for registering a storage address of an instruction to be tested, and an environment setting for setting an operating environment before execution of the instruction to be tested. means, an execution means for executing the instruction to be tested, and a checking means for comparing the execution result of the instruction to be tested executed by the execution means with an expected value to check for the presence or absence of an error;
A data processing device testing method including display means for displaying a test target instruction based on an address registered by the registration means as part of an error message when an error is detected by the checking means.