JPS63201744A - Memory access controller - Google Patents

Abstract

PURPOSE:To shorten the processing time in a memory access controller by reading out a data from a data part of a cache memory in parallel with an index of an address registering part of the cache memory when the preceding memory access request and a memory read-out request executing an access to the same level of a cache. CONSTITUTION:When a memory access request does not exist in a stage 3, and also, memory access requests of a stage 2 and a stage 1 are not issued by the same CPU, an output of a level holding register 109 holding a cache hit level of the preceding memory access request is compared with and a cache hit level of the memory access request of the stage 1. If they are equal, the memory access request of the stage 1 executes read-out of a data of a cache memory 10C simultaneously in parallel with an index of a cache memory address registering part 104, and stores a read-out data in a cache data register 10D by the next clock timing. In such a way, the processing time in a memory access controller can be shortened.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention has a set-associative type cache memory, and when a memory access request is received from each processing device, the request address, write, and request command are transferred to a pipe. It comes under line control, indexes the cache memory address registration section with the request address from the processing device stored in the address register, determines whether it is a catch hit or miss, and determines the catch hit level. The present invention relates to a memory access control device that executes processing.

[Conventional technology]

FIG. 3 is a block diagram of a conventional example of this type of memory access control device.

Memory access requests from each processing device 11f (CPU, 10P) are accepted by the memory access request receiving unit 102, and when one with a high priority is selected, the request address is stored in the address register 103. The cache memory (cache data registration unit) 10C of this memory access control device is of a set associative type, and the address registration unit 104 is indexed by the lower address stored in the address register 103, and the cache memory address registration unit 104 is indexed by the lower address stored in the address register 103. By comparing the read registration data with the upper address of address register 103 by comparator 105, it is determined whether the memory access request is a cache hit or a miss. The cache memory is made up of a plurality of levels (access units), and in the case of a cache hit, the comparison result is a match at one of the levels, that is, a cache hit, and there is no match at the other levels. When Carre Yumis hits, all levels will be inconsistent. The comparison results of each level in the comparator 105 are stored in the cache level register 106, and at the same timing, the lower address of the address register 103 is stored in the cache address register 1.
Stored in 0A. Then, in the next clock cycle, the cache level stored in the cache level register 106 to access the data registration section 10C of the cache memory is stored in the cache level register 107, and the lower address is stored in the cache level register 107. It is stored in the address register 10B. If the memory access request is a read request, the cache level register 10
The data in the cache memory data register 10C at the address indicated by the output of the cache address register 10B at the level indicated by 7 is read out and stored in the cache data register 10D in the next cycle. If the memory access request is a write request, the memory access request enters the pipeline in parallel with the index of the cache memory address registration unit 104, and the write data reception unit 120, data register 121.
The write data stored in the cache data register 123 via 122 is written to the address within the cash hit level of the indicated cache memory data registration section 10C in the same manner as when reading. The read data is sent from the data reply unit 10E to each request source processing device.

[Problems to be Solved by the Invention] When the conventional memory access control device described above receives a memory access request from each processing device, it indexes the cache memory address registration section under pipeline control. The cache memory data section is accessed by determining whether a memory access request is a hit or a miss and determining the hit level at the time of a hit, but the cache memory address registration section is similarly indexed using pipeline control for subsequent memory access requests. ,
A hit or miss and a hit level are determined and the cache memory data registration section is accessed. When a memory access request accesses, the cache memory address registration section is indexed, the hit level (same level) is determined, and the cache memory data registration section is accessed, in the same way as the preceding memory access request. You will have to repeat this action repeatedly.

Since it is desirable to shorten the processing time of a memory access request as much as possible, repeating the same process for each request will degrade the performance of memory access request processing.

[Means for solving problems]

The memory access control device of the present invention includes: a level holding register that holds a hit level at the time of cache hit; a comparator that compares data stored in the level holding register with input data to the level holding register; a first selector that selects a cache address supplied to a memory or a requested address from the address register; a second selector that selects a cache level supplied from a pipeline or an output of the level holding register; a third selector for selecting a request command supplied from the stage for reading the cache memory or a request command supplied from the first stage, and a cache address and cache hit level normally supplied from the pipeline; The memory access request exists in the stage where the memory access request information of each stage is obtained from the request command register in the pipeline where the request command of the memory access request issued from each processing unit is stored, and the cache memory is read. and if the memory access requests of stages other than this stage are not issued by the same processing device, the request address from the address register, the output of the level holding register, the request supplied from the first stage. 1st to select each command. Second
, a timing control unit that controls a third selector, and if the comparison result by the comparator is a match, sets the read data in a cache read data register that stores the read data from the cache memory, and sets the read data in the cache read data register that stores the read data from the cache memory, and sets the read data in the cache read data register that stores the read data from the cache memory, and register control means that holds the level holding register and does not set the read data in the cache read data register in the case of a mismatch, and sets the level holding register; and a reply control section that controls and sends the cache read data to the request source and outputs a reply signal to the request source.

[Effect]

If the subsequent cached memory access request is a memory read request that accesses the same level of the cache as the preceding memory access request, the data in the cache memory is read in parallel with the index of the address registration section of the cache memory. Since reading is performed from the section, the processing time within the memory access control device is shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an example of a computer system having a set associative cache memory.

Multiple processing devices CPtJ201t, 2012°10P
2051 and 2052 are connected to the MMLI 203 via the memory access control device 202 having the cache memory 204.
It is connected to the. Multiple processing devices CPLI2011.
2012. IOP 2051.

When a memory access request issued from the cache memory 2052 is selected by the memory access control unit @202 and the selected memory access request is cached, if the memory access request is a read request, the read from the cache memory 204 is performed. Data request source processing bag @cPLI20
11, 2012 or 1OP205z, 2052, and if it is a write request, the write data specified by the write request is written into the cache memory 204. Further, if the selected memory access request causes a cache miss, the memory access request is sent to the MMU 203, and if it is a read request, block data is returned to the requesting device via the memory access control device 203. In addition, if it is a write request, the block data of the corresponding address is first
Read from MU203, memory access control 81120
2 and writes the merged data to the cache memory code 11-204 of the memory access fi1111 device 202. MMU20 at cache miss
The latest data read from No. 3 is written to the cache memory 204 of the memory access control device 202.

FIG. 1 is a block diagram of memory access control device 202. As shown in FIG.

The general operation of this memory access control device 202 (determination of whether a selected memory access request is a cache hit or a miss, and data read/write operations of the cache memory 204) is different from the conventional memory access control device shown in FIG. It's the same. This embodiment focuses only on reading the cache memory (cache data registration unit 10C>IOC), and the write data reception unit 120
, data registers 121, 122, and cache data register 123 are not shown in FIG.
14 is also incorporated in the conventional memory access control device shown in FIG. 3, but is not shown in FIG. 3 because it is not particularly necessary for the explanation.

In this embodiment, level holding register 109. Comparator 10
8. Timing control section 10F, reply control section 110.
Selectors 115, 116, 117° selector control signal lines 118, 119. A cache data register control signal line 11A and an inverter 11B are added to the conventional example shown in FIG.

The memory access control device of this embodiment operates under pipeline control as in the conventional case. Under this pipeline control, the following processing conditions exist. First, same-CP
Memory access requests from u must be ordered, and subsequent requests must not be processed before preceding requests. Furthermore, memory access requests issued from the 10P 205 or 2052 do not need to maintain the order of processing. There is no need to maintain order among each processing device.

Next, the operation of this embodiment will be explained.

In the memory access control device 202, memory access requests from each processing device are received by the memory access reception unit 102.
When a memory access request with a high priority is selected, the request address of the selected memory access request is stored in the address register 103. Then, the cache memory address registration unit 104 is indexed by the lower address of the address register 103, and the cache memory address registration unit 104 is indexed by the lower address of the address register 103.
The read data from No. 4 is compared with the upper address of address register 103 by comparator 105 to determine whether it is a cache hit or a miss.

At the time of a cash hit, the cash hit level is indicated, and the cash hit level is stored in the cash hit level register 106 in the next clock cycle. Furthermore, the lower address of address register 103 is stored in cache address register 10A. At the same time, the cash hit level is also held in the level holding register 109. In the conventional memory access control device (FIG. 3), the output of the cache level hit register 106 is sent to the cache level register 107 and the cache 1 address register 1 is sent to the cache level register 107 at the next clock timing.
The output of 0A is stored in the cache address register 10B, and data from the cache memory 10G is read. In the case of this memory access control device, level holding register 1
indexed by the request address of the subsequent memory access request stored in the address register 103 within the same cycle in which the cash hit level was stored at 09;
A comparator 108 compares the determined cash hit level, which is the output of the comparator 105, with the output data of the level holding register 107. If the comparison result of the comparator 108 matches, that is, the output of the level holding register 109, which is the cash hit level of the preceding memory access request, and the output of the comparator 105, which is the cash hit level of the subsequent memory access request. If they are equal, a match notification signal is sent to the cache data register 10D via the signal line 11A, and if the outputs of the comparator 108 do not match, a mismatch notification signal is sent to the level holding register 109 via the inverter 11B. Here, the cache address and cache hit level given to the cache memory data registration section 10G are selected by the selector 115 and the selector 116, respectively. Generally, the outputs of the stage 3 cache address register 10B and cache level register 107 are selected, but under the following conditions, the level holding register 109
The lower address of the address register 103 is selected under the control of the timing controller controller 10F. ■Stage 3 cache address register 10B, cache level register 107. There is no memory access request in the request command register 113 or the like. and (2) the preceding stage 2 cache address register 10A, cache level register 106. Request command register 1
12 memory access requests are sent to subsequent stage 1 address registers 103 . When the request is not issued by the same CPU as the memory access request of the request command register 111, that is, under this condition, the output of the level holding register 109 and the lower address of the address register 103 are respectively output to the selector 116. It is selected by the selector 115 and supplied to the cache memory 10G. When the comparison result of comparator 108 is a match, a match notification signal is sent to cache data register 10D, and selector 115. Selector 11
The read data from the cache memory 10G at the address selected in step 6 is stored in the cache data register 10D at the next clock timing. When the result of comparator 108 is a mismatch, no match notification signal is sent to cache data register 10D, and cache data register 100 is not set. Further, a mismatch notification signal is sent to the level holding register 109, and the level holding register 1
The stored data of 09 is updated.

With the above operation, when there is no memory access request in stage 3 and the memory access requests in stage 2 and stage 1 are not issued by the same CPU,
If the output of the level holding register 109 that holds the cache hit level of the preceding memory access request and the cache hit level of the stage 1 memory access request are equal to -11:\-, then the stage 1 memory access request is In parallel with the indexing of the cache memory address registration unit 104, data is read from the cache memory 10G at the same time, and the read data is stored in the cache data register 10D at the next clock timing.

During the above operation, selector 115. As described above, the selector 116 is controlled by the timing control section 10F. The timing control unit 10F includes request command registers 111, 112, and 113 in the pipeline that store request commands for memory access requests issued from each processing device.
Information on the memory access request of each stage (valid state of request, write request/read request, request source device) is obtained from selector 115. Controls selector 116. For example, there is no memory access request in stage 3, and
When stage 2 and stage 1 are not memory access requests issued by the same CPU, and stage 1 is a read request, selector 115 and selector 116 select the lower address of address register 103 and level holding register 1.
The output of 07 is selected and the data in the cache memory 10C is read. The same is true when there is no memory access request in stages 2 and 3, and stage 1 is a cache read request. However, here, the cache data register IOD contains cache memory 1.
The 0C read data is stored only when the comparison result of the comparator 108 is a match. Further, at this time, the selector 117 is also controlled at the same time, and the contents of the request command register 111 are selected.

Next, the data read into the cache data register 10D is returned to the requesting device by the data reply unit 10E, and this control is performed by the reply control unit 110. The reply control unit 110 is the timing control unit 10
Receives reply timing information from F. The memory access request executed in the pipeline processing in the embodiment ends the pipeline processing two clock cycles faster than the general processing.

Then, taking this timing into consideration, the data reply section 10E is controlled to execute a reply to the data request source. Also, a reply signal is issued to the requesting device at the same timing.

The above is the operation of this embodiment, and in this way, the processing time within the memory access control device 202 can be shortened. Note that this is not the case when there is a cache miss or when accessing a level different from that of the preceding memory access request, and conventional pipeline processing is executed.

〔Effect of the invention〕

As explained above, in the present invention, when a subsequent cache memory read request received from each processing device accesses the same level of the cache as the preceding memory access request, the address registration section of the cache memory is By making it possible to read data at the corresponding level in the data section of the cache memory in parallel with the index, the processing time within the memory access control device for memory access requests received from each processing device is shortened, improving performance. It has the effect of increasing

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the memory access control device 202 in FIG. 2, FIG. 2 is a diagram showing an overview of a computer system including the memory access control device, and FIG. 3 shows a conventional example of the memory access control device. It is a block diagram. 102...Memory access request reception unit, 103...
Address register, 104... Cache memory address registration section, 105
．． 108...Comparator, 106...Cash hit level register, 107
... Cache level register, 109... Level holding register, 10A, 10B... Cache address register 10
G...Cache memory data registration section, 10D...
Cache data register, 10E...Data reply unit, 10F...Timing control unit, 110...Reply control unit, -2・1- 111-114...Request command register, 115-1
17...Selector, 118.119...Selector control signal line, 11A...
・Cache data register control signal line, 11B...
Inverter; 201...CPtJ. 202... Memory access control device, 203... Main memory unit (MMU), 204... Cache memory, 205... Input/output processing device (IOP). Patent applicant: NEC Corporation 5-, ”-22- Figure 2 Figure 3

Claims (1)

[Claims] It has a set associative cache memory,
When a memory access request from each processing device is accepted, the request address, write data, and request command are put under pipeline control, and the cache memory address registration section is indexed by the request address from the processing device stored in the address register. , determines cache hit or miss and determines cache hit level;
In a memory access control device that executes each process according to a request command, a level holding register that holds the hit level at the time of a cache hit, and a comparison that compares the data stored in the level holding register and the input data to the level holding register. a first selector that selects a cache address supplied from the pipeline to the cache memory or a requested address from the address register; and a first selector that selects a cache hit level supplied from the pipeline or the output of the level holding register. a second selector that selects a request command supplied from the stage that reads the cache memory or a request command supplied from the first stage, and a cache address that is normally supplied from the pipeline, A request command for memory access requests issued from each processing device is stored by selecting a hit level.
A processing device that obtains memory access request information for each stage from the request command register in the pipeline, that there is no memory access request in the stage that reads the cache memory, and that the memory access requests of the stages other than that stage are the same. If the request command is not issued from the address register, the first, second, and third selectors are configured to select the request address from the address register, the output of the level holding register, and the request command supplied from the first stage, respectively. If the comparison result by the timing control unit to control and the comparator match, the read data is set in the cache read data register that stores the read data from the cache memory, the level holding register is held, and the mismatch is detected. register control means that sets the level holding register without setting the read data in the cache read data register; and upon receiving reply timing information from the timing control section, controls the data reply section to read the cache read data. A memory access control device comprising: a reply control section that sends data to a request source and outputs a reply signal to the request source.