JPS63201750A - Bus monitoring system - Google Patents

Abstract

PURPOSE:To obtain a simple bus monitoring system for curtailing a hardware, by counting a bus request signal outputted at a prescribed time interval for a refresh operation, and outputting a bus abnormal occupancy informing signal, as time-over, when the refresh operation is not completed even after a prescribed number has been counted. CONSTITUTION:In a multi-master system having plural masters, an abnormal occupancy of a system bus is prevented by providing a bus monitoring part, but since the bus monitoring part is provided independently from other unit, the cost becomes high. Therefore, this system is provided with a counting means 30 which counts a bus request signal 50 outputted for a refresh operation, and also, reset by a completing signal 52 of a storage holding operation, and an output means 31 for outputting a bus abnormal occupancy informing signal 53, when the counting means 30 has counted a prescribed number of bus request signals 50. In such a way, this system can be constituted of a simple hardware.

Description

[Detailed Description of the Invention] (Summary) In a multi-mask system that performs a memory retention (refresh) operation of a dynamic memory with bus permission, the bus request signals output at predetermined time intervals for the refresh operation are counted. , when the refresh operation is not completed even after counting a predetermined number of times, a bus abnormal occupancy notification signal is output as a time-over.

[Industrial application field]

The present invention relates to a data processing device, and more particularly to an improvement in a bus monitoring method for a system bus shared by a plurality of Hasmasks (hereinafter referred to as masks).

In a multi-mask system in which there are a plurality of masks that control a system bus, a bus monitoring unit is provided to prevent abnormal occupation of the system bus due to a hardware abnormality in each mask.

However, since this bus monitoring section is conventionally prepared independently from other units, there is a problem that the hardware is expensive, and a simple bus monitoring system is required.

[Conventional technology]

FIG. 4 is an explanatory diagram of a conventional bus monitoring system.

In the figure, ① is the central processing unit CPU, A and B are masks that control the common bus (system bus) 100 and access the common memory 6 instead of the CPUI, 4 is a bus arbitration unit, and each mask 5 is a bus monitoring unit that arbitrates bus requests output from A, B, etc. and grants usage rights;
A device that outputs an interrupt signal to the CPUI and releases the common bus 100 due to abnormal processing, etc. 6 is a common memory commonly used by the CPUI and each mask A and B, and is composed of Guinami Soku RAM (DRAM). 7 is a refresh unit that performs refresh control of the DRAM 6;

In the above system, each mask A and B outputs a bus request to the bus arbitration unit 4 and accesses the common memory 6 after obtaining the right to use the common bus 100.

If some hardware failure occurs in the mask that has obtained the right to use the bus and the common bus 100 remains occupied, other masks and CPUs will not be able to use the common bus 100, and the entire system will be affected. is in standby mode.

The bus monitoring unit 5 is provided to monitor the above-mentioned abnormal occupancy, and counts the time from the rise of the address strobe signal 54 outputted to the common bus 100, for example, and is reset by the response signal 55 in response to the access. When the timer 5a counts a predetermined time, an interrupt signal 56 is output to the CPUI and a hardware reseller I signal is output to each mask to open the common bus 100 as a time-over.

[Problem that the invention seeks to solve]

As mentioned above, in a multi-mask system that has multiple masks, a bus monitoring unit is provided to prevent abnormal occupancy of the system bus, but since the bus monitoring unit is provided independently from other units, the cost is high. There is a problem.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a simple bus monitoring method that reduces hardware.

[Means for solving problems]

For the above purpose, the bus monitoring system of the present invention counts the bus request signals (50) output for the refresh operation and completes the memory retention operation, as shown in FIG. a counting means (30) that is reset by a signal (52); and an output means (31) that outputs a bus abnormal occupancy notification signal (53) when the counting means (30) counts a predetermined number of the bus request signals (50). ).

[Effect]

The memory retention operation (refresh operation) of the memory 12 used as a common memory for each mask is performed at predetermined time intervals with bus permission obtained.

Therefore, the bus request signal 50 for obtaining permission to use the bus is
If the refresh operation is not completed within a predetermined time (counting the bus request signal 50) after is output, it is determined that the system bus 100 is abnormally occupied by another bus mask, and a bus abnormal occupation notification is issued. A signal 53 is output.

This refresh operation is normally performed at a cycle of 2 to 4 mS, but since the memory 12 is composed of rows and columns, and the memory chips are sequentially selected and refreshed row by row, the bus request signal 50 is It is output at time intervals of about several μs.

A counting means 30 is provided which counts the bus request signal 50 and is reset by a refresh completion signal 52, and when the counting means 30 counts a predetermined number, an output means 31 outputs a bus abnormal occupancy notification signal 53 as a time-over.

In response to this bus abnormality occupancy notification signal 53, the processor performs predetermined abnormality processing, each mask is hardware reset, and the system bus 100 is released.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1 to 3.

This embodiment shows an example in which the bus request signal 50 is counted twice, that is, the completion of the refresh operation is monitored for each refresh request. FIG. 2 is a block diagram of the bus monitoring section of the embodiment, and FIG. The operation time chart is shown below.

In FIG. 2, reference numeral 10 denotes a refresh request generating section, which outputs a refresh request signal (bus request signal) 50 at predetermined time intervals (for example, 16 μs).

This refresh request signal 50 is output as a bus request signal 50 to the bus monitoring section 21 and the bus arbitration section 4.

Reference numeral 11 denotes a refresh execution section, which includes DRAM control means for controlling the memory DRAM 12 when accessed from each mask A and B, and refresh execution means.

That is, when the DRAM 12 is accessed from the common bus 100, the row address data and column address data are outputted through the multiplexer MPX14 and the DR
When AM12 is accessed and bus use permission signal 51 is input, MPX is switched and refresh counter 1 is input.
3, outputs row address data and instructs refresh operation.

The timing generator 15 outputs the timing generator for the above control, and also outputs a refresh completion signal 52 after a predetermined time has elapsed since the refresh instruction.

Reference numeral 12 designates a memory DRAM that stores the address data output by the refresh execution unit 11 in an address buffer (not shown), and also stores the address data output by the refresh execution unit 11 in an address buffer (not shown), and also stores the address data output by the refresh execution unit 11.
1B and column decoder C/D16 select one bit of memory cell 19 and read/write data.

When the timing generator 15 outputs the row address strobe signal RAS and instructs a refresh operation, the memory chip at the designated row address is selected and refreshed.

21 is a bus monitoring unit according to an embodiment of the present invention.

Note that the bus permission signal 51 corresponds to the bus request signal 50, and the same reference numerals represent the same objects throughout the other figures.

The bus monitoring section 21 includes a flip-flop FF22 (corresponding to the counting means 30), an FF24, and an AND circuit 23 (corresponding to the output means 31), which are connected as shown. That is, as shown in FIG. 3, the operation is as follows.

The Q output of the FF 22 is set to "L" by the bus request signal 50 output from the refresh request generating section 10, and is reset when the refresh completion signal 52 is output.

Therefore, if the refresh completion signal 52 is not output,
Since the Q output of FF22 is “L”, AND circuit 23
The next bus request signal 50 is input to the FF 24 via
The Q output of the FF 24 is set to "1" and a bus abnormal occupancy notification signal (CPU interrupt signal and mask reset signal) 53 is output.

The bus monitoring operation will be explained below with reference to FIG.

(11 The refresh request generation unit 10 generates a bus request signal 50
is output to the bus arbitration unit 4.

(2) In the bus monitoring unit 21, the FF 22 counts the bus request signal 50, and the Q output is set to "1".

(3) When the bus arbitration unit 4 outputs the bus permission signal 51, the refresh execution unit 11 outputs row address data and a strobe signal RAS to instruct the DRAM 12 to perform a refresh operation.

(4) After a predetermined period of time has elapsed, a refresh completion signal 52 is output from the refresh execution unit 11, and the FF 22 is reset.

If the common bus 100 is normal, the above operation is repeated and the Q output of the FF 24 remains in the "0" state.

(5) When the common lotus 100 is abnormally occupied by the mask and the bus permission signal 51 is not responded to, after a predetermined time (1
6 μs), the bus request signal 50 is output again, and the FF 24
is set and a bus abnormal occupancy notification signal 53 is output.

” In the above, the refresh time interval is set to the bus occupancy timeover, but if you want to increase the time interval even further, use the FF
22 may be replaced by a plurality of flip-flops to count a predetermined number of bus request signals 50.

As described above, the method of monitoring the system bus 100 based on the hash request signal 50 output for refresh operation and the refresh completion signal 52 can be realized with a simple circuit. By incorporating it into the system, costs can be significantly reduced.

〔Effect of the invention〕

The present invention provides a lotus monitoring method that monitors whether the dynamic memory has been refreshed normally and determines abnormal occupancy of the lotus.Since it can be configured with simple hardware, the cost effect is extremely large. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram of a bus monitoring section according to an embodiment, FIG. 3 is a time chart of monitoring operation, and FIG. 4 is a diagram illustrating a conventional lotus monitoring system. In the figure, 1 is a central processing unit CPU, 4 is a bus arbitration unit, 5 is a bus monitoring unit, 5a is a timer, and 6 is a dynamic memory DRAM. 11 a refresh execution unit; 12 a dynamic memory DRAM; 13 is a refresh counter, and 14 is a multiplexer MPX. 15 is a timing generator; 16 is a column decoder C-D. 18 is a row decoder R-D. 19 is a memory cell, 21 is a bus monitoring unit, 22.24 is a fringe block, 23 is a gate, 50 is a bus request signal (refresh request signal) output for refresh operation, 51 is a hash permission signal, 52 is a refresh 53 is a bus abnormal occupancy notification signal (CPU interrupt signal, hardware reset signal), 54 is an address strobe signal, 55 is a response signal, and 56 is an interrupt signal.

Claims (1)

[Scope of Claims] A system bus (100) connected to a dynamic memory (12) that performs a memory retention operation upon obtaining permission to use the bus based on a bus request signal (50) output at predetermined time intervals.
A bus monitoring method in which the bus request signal (50
) and also outputs the memory retention operation completion signal (5
2); and an output means (31) for outputting a bus abnormal occupancy notification signal (53) when the counting means (30) counts a predetermined number of the bus request signals (50). is provided, and the system bus (1
A bus monitoring method characterized by monitoring 00).