JPS6320191U - - Google Patents

Info

Publication number
JPS6320191U
JPS6320191U JP11145686U JP11145686U JPS6320191U JP S6320191 U JPS6320191 U JP S6320191U JP 11145686 U JP11145686 U JP 11145686U JP 11145686 U JP11145686 U JP 11145686U JP S6320191 U JPS6320191 U JP S6320191U
Authority
JP
Japan
Prior art keywords
display element
matrix display
electrodes
substrate
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11145686U
Other languages
English (en)
Other versions
JPH0434548Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986111456U priority Critical patent/JPH0434548Y2/ja
Publication of JPS6320191U publication Critical patent/JPS6320191U/ja
Application granted granted Critical
Publication of JPH0434548Y2 publication Critical patent/JPH0434548Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Description

【図面の簡単な説明】
第１図は、本考案のマトリツクス表示素子の平
面図。第２図は、従来のマトリツクス表示素子の
平面図。第３図は、本考案のマトリツクス表示素
子の回路基板との接続部分を示す拡大断面図。 マトリツクス表示素子：１，１１、信号電極の
端子：２Ａ，２Ｂ，１２Ａ，１２Ｂ、導電ゴムコ
ネクター：３Ａ，３Ｂ，１３Ａ，１３Ｂ、回路基
板：４Ａ，４Ｂ，１４Ａ，１４Ｂ、走査電極の端
子：５Ａ，５Ｂ，１５Ａ，１５Ｂ、可撓性基板：
６，１６Ａ，１６Ｂ。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 複数組の走査電極を有する基板と信号電極
    を有する基板とを有し、両基板間に電気光学的表
    示媒体を挾持し、両電極の端子を駆動回路素子を
    配置した回路基板に接続してなるマトリツクス表
    示素子において、該複数組の走査電極の端子が夫
    々表面に導電性膜を形成した可撓性基板に接続さ
    れ、該複数の可撓性基板が走査電極の端子と反対
    の側でほぼ重なるように配置されて回路基板に接
    続されていることを特徴とするマトリツクス表示
    素子。 (2) ２組の可撓性基板がＹ字状に配置されてい
    る実用新案登録請求の範囲第１項記載のマトリツ
    クス表示素子。
JP1986111456U 1986-07-22 1986-07-22 Expired JPH0434548Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986111456U JPH0434548Y2 (ja) 1986-07-22 1986-07-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986111456U JPH0434548Y2 (ja) 1986-07-22 1986-07-22

Publications (2)

Publication Number Publication Date
JPS6320191U true JPS6320191U (ja) 1988-02-09
JPH0434548Y2 JPH0434548Y2 (ja) 1992-08-17

Family

ID=30991397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986111456U Expired JPH0434548Y2 (ja) 1986-07-22 1986-07-22

Country Status (1)

Country Link
JP (1) JPH0434548Y2 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56121018A (en) * 1980-02-28 1981-09-22 Sharp Corp Terminal treating method for multilayer liquid-crystal panel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56121018A (en) * 1980-02-28 1981-09-22 Sharp Corp Terminal treating method for multilayer liquid-crystal panel

Also Published As

Publication number Publication date
JPH0434548Y2 (ja) 1992-08-17

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