JPS63202955A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63202955A JPS63202955A JP3615687A JP3615687A JPS63202955A JP S63202955 A JPS63202955 A JP S63202955A JP 3615687 A JP3615687 A JP 3615687A JP 3615687 A JP3615687 A JP 3615687A JP S63202955 A JPS63202955 A JP S63202955A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- insulating film
- film
- resistors
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 229920005591 polysilicon Polymers 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法に関し、特に抵抗体の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a resistor.
（ロ）従来の技術
一般に集積回路に用いられる抵抗体は特開昭６１−１９
１０６０号公報（ＨＯＩＬ２７１０４）に詳述されてい
る。(b) Conventional technology Resistors generally used in integrated circuits are
It is described in detail in Publication No. 1060 (HOIL27104).
先ず第２図（Ａ）に示す如く、一導電型の半導体基板（
２１）を用意し、前記半導体基板（２１）上に熱酸化法
等で酸化シリコン等の絶縁膜（２２）を形成する。First, as shown in FIG. 2(A), a semiconductor substrate of one conductivity type (
21) is prepared, and an insulating film (22) made of silicon oxide or the like is formed on the semiconductor substrate (21) by thermal oxidation or the like.
次に第２ＵｇＪ（Ｂ）に示す如く、前記絶縁膜（２２）
上にＣＶＤ法等で第１抵抗体の抵抗体材料となるポリシ
リコン膜（２３）を形成する。Next, as shown in the second UgJ (B), the insulating film (22)
A polysilicon film (23) which will become the resistor material of the first resistor is formed thereon by CVD or the like.
次に第２図（Ｃ）に示す如く、前記ＣＶＤ法等で形成き
れたポリシリコン膜（２３）と前記絶ｉ膜（ｚｚ）とを
写真蝕刻法でパターン化し、前記半導体基板（２１）を
露出させる。Next, as shown in FIG. 2(C), the polysilicon film (23) completely formed by the CVD method or the like and the insulating film (zz) are patterned by photolithography, and the semiconductor substrate (21) is patterned. expose.
続いて第２図（Ｄ）に示す如く、前記第１抵抗体（２３
）・・・（２３）をマスクとして、この第１抵抗体（２
３）・・・（２３）の間（前記露出した半導体基板（２
１））にイオン注入し第２抵抗体（２４）・・・（２４
）を形成する。Next, as shown in FIG. 2(D), the first resistor (23
)...(23) as a mask, this first resistor (2
3)...(23) (the exposed semiconductor substrate (2)
1)), and the second resistor (24)...(24
) to form.
更に第２図（Ｅ）に示す如く、イオン注入した半導体基
板（２１）を熱酸化処理し前記半導体基板（２１）表面
に酸化シリコン膜（２５）を形成する。Furthermore, as shown in FIG. 2(E), the semiconductor substrate (21) into which ions have been implanted is subjected to thermal oxidation treatment to form a silicon oxide film (25) on the surface of the semiconductor substrate (21).
最後に第２図（Ｆ）に示す如く、第１抵抗体（２３）・
・・（２３）および第２抵抗体（２４）・・・（２４）
のコンタクト孔となる箇所を写真蝕刻法等で開孔し電極
（２６）を接続していた。Finally, as shown in Figure 2 (F), the first resistor (23)
...(23) and second resistor (24)...(24)
A contact hole was formed using photolithography or the like, and an electrode (26) was connected thereto.
（ハ）発明が解決しようとする問題点
上述の如き製造方法で形成された抵抗体（２３〉・・・
（２３）は上層部が切立っているためシリコン酸化膜（
２５）を均一にできず、このシリコン酸化膜（２５）上
の電極＜２６）と抵抗体（２３）がショートしたり、ス
テップ部が断線を生じやすく、電極やシリコン酸化膜を
厚く形成する必要があった。(c) Problems to be solved by the invention Resistor elements (23) formed by the above-mentioned manufacturing method
(23) has a steep upper layer, so the silicon oxide film (
25) cannot be made uniform, shorting occurs between the electrode <26) on this silicon oxide film (25) and the resistor (23), and the step part is prone to disconnection, so it is necessary to form the electrode and silicon oxide film thickly. was there.
更には前記抵抗体（２３）・・・（２３）で高抵抗値を
得る時は、抵抗体の寸法を長くするか、断面積を小さく
する必要があった。しかし断面積を小さくするのは加工
限界があり精度上問題を有し、寸法を長くするとチップ
面積を大きくしてしまう。更にはシート抵抗を大きくし
て高抵抗を形成すると室圧−電流特性が非線型となり抵
抗体として形成するには問題を有していた。Furthermore, in order to obtain a high resistance value with the resistors (23) (23), it was necessary to increase the dimensions of the resistor or reduce the cross-sectional area. However, reducing the cross-sectional area has a processing limit and poses a problem in accuracy, and increasing the dimension increases the chip area. Furthermore, when the sheet resistance is increased to form a high resistance, the chamber pressure-current characteristics become non-linear, which poses a problem in forming a resistor.
（二〉問題点を解決するための手段
本発明は上述の問題点に鑑みてなされ、一導電型の半導
体基板（１）上に第１の絶縁膜（２）を被覆する工程と
、この第１の絶縁膜（２）上に第１の抵抗体（３）を被
覆する工程と、この第１の抵抗体（３）上に第２の絶縁
膜（４）を被覆する工程と、この第２の絶縁膜（４）上
に所定形状のホトレジスト膜（５）を形成する工程と、
このホトレジスト膜（５）を介して前記第２の絶縁膜（
４）および第１の抵抗体（３）を蝕刻して前記第１の抵
抗体（３）・・・（３〉をテーパーエツチングする工程
と、前記ホトレジスト膜（５）を除去し第３の絶縁膜（
６）を前記半導体基板（１）上に被覆する工程と、この
第３の絶縁膜（６）上に第２の抵抗体く７）を被覆する
工程と、この第２の抵抗体（７）上に第４の絶縁膜（８
）を被覆する工程と、この第４の絶縁膜（８）上に所定
形状のホトレジスト膜（９）を形成する工程と、このホ
トレジスト膜（９）を介して前記第４の絶縁膜（８）お
よび第２の抵抗体く７）を蝕刻して前記第２の抵抗体（
７）・・・（７）を前記第１の抵抗体（３）・・・（３
）とは逆のテーパー形状にエツチングする工程と、前記
ホトレジスト膜（９）を除去し第５の絶縁膜（１０）を
前記半導体基板（１）上に被覆する工程と、前記第１の
抵抗体（３〉・・・（３）および第２の抵抗体（７）・
・・（７）と電気的に接続される電極（１１）を形成す
る工程とにより解決するものである。(2) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a step of coating a first insulating film (2) on a semiconductor substrate (1) of one conductivity type; A step of covering the first resistor (3) on the first insulating film (2), a step of covering the second insulating film (4) on the first resistor (3), and a step of covering the first resistor (3) with the second insulating film (4). forming a photoresist film (5) in a predetermined shape on the insulating film (4) of No. 2;
The second insulating film (
4) and a step of etching the first resistor (3) to taper-etch the first resistor (3)...(3), and removing the photoresist film (5) and etching the third insulating film. film(
6) on the semiconductor substrate (1); a step of covering the third insulating film (6) with a second resistor (7); and a step of coating the second resistor (7) on the third insulating film (6). A fourth insulating film (8
), a step of forming a photoresist film (9) of a predetermined shape on this fourth insulating film (8), and a step of coating the fourth insulating film (8) through this photoresist film (9). and the second resistor (7) by etching the second resistor (7).
7)...(7) to the first resistor (3)...(3
), a step of removing the photoresist film (9) and covering the semiconductor substrate (1) with a fifth insulating film (10), and a step of etching the photoresist film (9) into a tapered shape opposite to that of (3>...(3) and second resistor (7).
This problem is solved by (7) and the step of forming the electrode (11) to be electrically connected.
（ホ）作用
ここで例えば第２の絶縁膜（４）をシリコン窒化膜、第
１の抵抗体（３）をポリシリコンとし、一般的なプラズ
マエツチング用のＣＦ４（０，ガスが１０％入る）ガス
を使用すると、シリコン窒化膜（４）の方がポリシリコ
ン膜（３）より約２倍エツチングレートが高くなるので
、前記シリコン窒化膜（４）の膜厚を制御して形成して
おけば、テーパー角を制御して抵抗体（３）・・・（３
）をエツチングできる。(E) Function Here, for example, the second insulating film (4) is a silicon nitride film, the first resistor (3) is polysilicon, and CF4 (0, 10% gas is included) for general plasma etching is used. When a gas is used, the etching rate of the silicon nitride film (4) is approximately twice as high as that of the polysilicon film (3), so if the thickness of the silicon nitride film (4) is controlled in advance. , resistor (3)...(3
) can be etched.
従って第１図（Ｃ）に示す如く、抵抗体（３）・・・（
３）の上層部は勾配がゆるやかになるために、前記抵抗
体（３）・・・（３）上に第３の絶縁膜（６）、第２の
抵抗体（７）を形成してもショートや断線を防止できる
。Therefore, as shown in FIG. 1(C), the resistor (3)...(
3) Since the upper layer has a gentle slope, even if the third insulating film (6) and the second resistor (7) are formed on the resistor (3)...(3), Can prevent short circuits and disconnections.
更には同様な方法を使って第１図（Ｅ）に示す如く、前
記第２の抵抗体（７）・・・（７）を前記第１の抵抗体
（３）・・・（３）間に絶縁膜（６）を介して形成し、
また前記第２の抵抗体（７）・・・（７）は前記第１の
抵抗体（３）・・・（３）とは逆向きのテーパー形状に
形成するために全体としてはほぼ平坦な表面となり、そ
の後に第５の絶縁膜（１０）および電極（１１）を形成
しても良好に形成できる。Furthermore, using a similar method, as shown in FIG. 1(E), the second resistors (7)...(7) are connected between the first resistors (3)...(3). formed through an insulating film (6),
Further, the second resistors (7)...(7) are formed in a tapered shape in the opposite direction to the first resistors (3)...(3), so that the second resistors (7)...(7) are generally flat as a whole. Even if the fifth insulating film (10) and the electrode (11) are formed after that, the fifth insulating film (10) and the electrode (11) can be formed satisfactorily.
また加工限度でテーパーエツチングすると従来の断面積
よりも小さくなる抵抗体を形成できるので高抵抗値が得
られチップの占有率も小さくでき、更には第１の抵抗体
（３）・・・（３）間に第２の抵抗体（７）・・・（７
）を設置できるので抵抗体を高密度に設置でき、イオン
注入条件等によっては前記抵抗体を電極としても使用で
きるので電極配線も高密度に形成できる。In addition, if taper etching is performed within the processing limit, it is possible to form a resistor whose cross-sectional area is smaller than that of conventional resistors, resulting in a high resistance value and a reduction in chip occupancy. ) between the second resistor (7)...(7
) can be installed, so the resistors can be installed at a high density, and depending on the ion implantation conditions, the resistors can also be used as electrodes, so the electrode wiring can also be formed at a high density.
（へ）実施例
以下に本発明である半導体装置の製造方法を第１図を参
照しながら詳述する。(F) EXAMPLE The method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIG.
先ず第１図（Ａ）に示す如く、一導電型の半導体基板（
１）を用意しこの半導体基板（１）上に熱酸化法等で酸
化シリコン等の第１の絶縁膜（２）を形成した後に、こ
の第１の絶縁膜（２）上に第１の抵抗体（３）を被覆す
る工程がある。First, as shown in FIG. 1(A), a semiconductor substrate of one conductivity type (
1) is prepared and a first insulating film (2) made of silicon oxide or the like is formed on this semiconductor substrate (1) by thermal oxidation method or the like, and then a first resistor is formed on this first insulating film (2). There is a step of coating the body (3).
ここではノンドープのポリシリコン膜（３）をＣＶＤ法
で約５０００人の厚さく厚さは抵抗値により変える）に
形成し、その後でリンイオン（Ｐ＋）を例えば１００Ｘ
１０’ｅＶ、１．５Ｘ１０”ｃｍ−”ｃ７）条件でイオ
ン注入する。ただしこのイオン注入条件はあくまでも１
例であり、種々のイオン注入条件で抵抗体（３）の抵抗
値を制御できるので他のイオン注入条件で注入しても良
い。更にはイオン注入後の熱処理はパターン形成後にす
る。Here, a non-doped polysilicon film (3) is formed using the CVD method to a thickness of about 5,000 mm (the thickness varies depending on the resistance value), and then phosphorus ions (P+) are
Ion implantation is performed under the conditions of 10'eV, 1.5×10''cm-''c7). However, this ion implantation condition is only 1.
This is an example, and since the resistance value of the resistor (3) can be controlled under various ion implantation conditions, implantation may be performed under other ion implantation conditions. Furthermore, heat treatment after ion implantation is performed after pattern formation.
次にこの第１の抵抗体（３〉上に第２の絶縁膜（４）で
あるシリコン窒化膜を被覆し、この第２の絶縁膜（４）
上に所定形状のホトレジスト膜（５）を形成する工程と
がある。Next, a silicon nitride film which is a second insulating film (4) is coated on this first resistor (3), and this second insulating film (4)
There is a step of forming a photoresist film (5) of a predetermined shape thereon.
ここでシリコン窒化膜はプラズマＣＶＤ法で被覆され、
約５００〜１０００人の厚さで形成される。またこのシ
リコン窒化膜の厚きは後の工程であるテーパーエツチン
グの際、ホトレジストと抵抗体の間へのガスの回り込み
を変えテーパー角を変えることができる。更にはここで
ホトレジスト膜（５）はポジ型を用い、ホトレジスト膜
（５）の形成される間隔およびホトレジスト膜の幅で形
成される抵抗体の抵抗値が左右される。Here, the silicon nitride film is coated by plasma CVD method,
Formed with a thickness of about 500-1000 people. Furthermore, the thickness of this silicon nitride film can change the taper angle by changing the flow of gas between the photoresist and the resistor during taper etching, which is a later step. Furthermore, the photoresist film (5) here uses a positive type, and the resistance value of the resistor formed is influenced by the interval at which the photoresist film (5) is formed and the width of the photoresist film.
次に第１図（Ｃ）に示す如く、このホトレジスト膜（５
）を介して前記第２の絶縁膜（４）および第１の抵抗体
（３）を蝕刻して前記第１の抵抗体（３）をテーパーエ
ツチングする工程がある。Next, as shown in FIG. 1(C), this photoresist film (5
), there is a step of etching the second insulating film (4) and the first resistor (3) through the etching process to taper-etch the first resistor (3).
７一
本工程は本発明の第１の特徴となる工程であり、ここで
は例えば微細加工に適した平行平板型のプラズマエツチ
ング装置を使用し、一般的なＣＦ４（０，ガスが１０％
入る）を使用する。このガスはポリシリコンとシリコン
窒化膜のエツチングレートに差を出し、シリコン窒化膜
はポリシリコンの２倍となる。またシリコン窒化膜は約
５００〜１０００人の厚さとし、今回は７００人とした
。The 7-step process is the first characteristic step of the present invention. Here, for example, a parallel plate type plasma etching apparatus suitable for microfabrication is used, and a common CF4 (0, gas is 10%
Enter). This gas produces a difference in the etching rate between polysilicon and silicon nitride, with the etching rate of silicon nitride being twice that of polysilicon. The thickness of the silicon nitride film was approximately 500 to 1,000, and this time it was 700.
上述の条件の下でエツチングすると先ずシリコン窒化膜
（４）が蝕刻されて、その後にポリシリコン（３）が蝕
刻されるのでポリシリコン抵抗体に約４０〜５０°のテ
ーパーを形成することが可能となる。前述したようにこ
こでシリコン窒化膜（４）の厚さを変えることでシリコ
ン窒化膜およびポリシリコンの上層部のエツチング状態
を変えられる（ガスの回り込みが変化する）のでポリシ
リコンのテーパー角を変えられる。またここではシリコ
ン窒化膜＜４）を後で完全に除去しているが、除去しな
くても良く更に絶縁耐圧を向上できる。When etching is performed under the above conditions, the silicon nitride film (4) is etched first, and then the polysilicon (3) is etched, so it is possible to form a taper of about 40 to 50 degrees in the polysilicon resistor. becomes. As mentioned above, by changing the thickness of the silicon nitride film (4), the etching state of the upper layer of the silicon nitride film and polysilicon can be changed (the gas circulation changes), so the taper angle of the polysilicon can be changed. It will be done. Further, although the silicon nitride film <4) is completely removed later, it is not necessary to remove it and the dielectric breakdown voltage can be further improved.
次に第１図（Ｄ）に示す如く、前記ホトレジスト膜（５
）を除去し第３の絶縁膜（６）を前記半導体基板（１）
上に被覆する工程と、この第３の絶縁膜（６）上に第２
の抵抗体く７）を被覆する工程と、この第２の抵抗体く
７）上に第４の絶縁膜（８）を被覆する工程と、この第
４の絶縁膜（８）上に所定形状のホトレジスト膜（９）
を形成する工程とがある。Next, as shown in FIG. 1(D), the photoresist film (5
) and remove the third insulating film (6) from the semiconductor substrate (1).
A second insulating film (6) is coated on the third insulating film (6).
a process of coating the second resistor element (7) with a fourth insulating film (8); and a process of coating the fourth insulating film (8) with a predetermined shape. photoresist film (9)
There is a step of forming.
ここで本工程は前述同様に第３の絶縁膜（６）はＣＶＤ
法で酸化シリコン膜を形成し、第２の抵抗体（７）は前
述同様にポリシリコン膜をＣＶＤ法で形成しイオン注入
処理され、第４の絶縁膜（８）はシリコン窒化膜で形成
される。またホトレジスト膜〈９）は前記第１の抵抗体
（３）・・・（３）の間に形成されるようにし、第１図
（Ｅ）の如くこの第１の抵抗体（３）・・・（３）間に
第２の抵抗体（７）・・・（７）が形成されるようにす
る。Here, in this step, the third insulating film (6) is formed by CVD as described above.
The second resistor (7) is formed with a polysilicon film using the CVD method and subjected to ion implantation treatment in the same manner as described above, and the fourth insulating film (8) is formed with a silicon nitride film. Ru. Further, the photoresist film (9) is formed between the first resistors (3)...(3), as shown in FIG. 1(E). - The second resistor (7)...(7) is formed between (3).
更に第１図（Ｅ）に示す如く、このホトレジスト膜〈９
）を介して前記第４の絶縁膜（８）および第２の抵抗体
く７〉を蝕刻して前記第２の抵抗体く７）・・・（７〉
を前記第１の抵抗体（３）・・・（３）とは逆のテーパ
ー形状にエツチングする工程がある。Furthermore, as shown in FIG. 1(E), this photoresist film <9
) through etching the fourth insulating film (8) and the second resistor 7) to form the second resistor 7)...(7)
There is a step of etching the first resistor (3) into a tapered shape opposite to that of the first resistor (3).
本工程は本発明の第２の特徴とする工程であり、前記第
２の抵抗体く７）・・・（７）を前記第１の抵抗体（３
）・・・（３）とは逆テーパーの形状とし、半導体基板
表面をほぼ平坦に形成することにある。ここで第１図（
Ｄ）の如くシリコン窒化膜（８）が表面に露出されてお
り、前述のエツチング装置、エツチングカスを使用する
ことで、先ずシリコン窒化膜の露出部が蝕刻されてその
下に形成されているポリシリコンが蝕刻され、徐々にホ
トレジスト膜（９）の膜が蝕刻されてゆく。従ってポリ
シリコンはほぼ平坦となり後の工程で電極や抵抗体を形
成する際にショートや断線が防止できる。This step is the second characteristic step of the present invention, in which the second resistor (7)...(7) is connected to the first resistor (3).
)...(3) is to have an inversely tapered shape and to form a substantially flat surface of the semiconductor substrate. Here, Figure 1 (
As shown in D), the silicon nitride film (8) is exposed on the surface, and by using the etching device and etching scum mentioned above, the exposed part of the silicon nitride film is first etched and the polygon formed below is etched away. The silicon is etched and the photoresist film (9) is gradually etched. Therefore, the polysilicon becomes substantially flat, and short circuits and disconnections can be prevented when electrodes and resistors are formed in later steps.
最後に第１図（Ｆ）に示す如く、前記ホトレジスト膜（
９）を除去し第５の絶縁膜（１０）を前記半導体基板り
１）上に被覆する工程と、前記第１の抵抗体（３）・・
・（３）および第２の抵抗体（７）・・・（７）と電気
的に接続される電極（１１）を形成する工程とがある。Finally, as shown in FIG. 1(F), the photoresist film (
9) and covering the semiconductor substrate 1) with a fifth insulating film (10), and the first resistor (3)...
- (3) and the second resistor (7)... There is a step of forming an electrode (11) electrically connected to (7).
ここでは第１図（Ｅ）で半導体基板表面を平坦にしたた
め前記第５の絶縁膜（１０）および電極（１１）を良好
に形成できる。Here, since the surface of the semiconductor substrate is made flat as shown in FIG. 1(E), the fifth insulating film (10) and the electrode (11) can be formed satisfactorily.
また平坦化にするため、複数の抵抗体を形成しであるが
、これを電極として使用しても良いし、電極や抵抗体と
して使用せずただ平坦化するための膜として使用しても
良い。Also, in order to achieve flattening, multiple resistors are formed, but these may be used as electrodes, or they may be used simply as a film for flattening without being used as electrodes or resistors. .
（ト）発明の効果
本発明は以上の説明からも明らかな如く、抵抗体と電極
のショートや断線を防止し素子の高圧化や高歩留りを達
成できる。(g) Effects of the Invention As is clear from the above description, the present invention can prevent short-circuits and disconnections between resistors and electrodes, and can achieve high voltage and high yield of devices.
またチップ面積に対する抵抗体の占有面積を小さくでき
るので、抵抗体をより高密度に実装できチップ面積を小
さくできる。Furthermore, since the area occupied by the resistor relative to the chip area can be reduced, the resistor can be mounted more densely and the chip area can be reduced.
更には抵抗体をイオン注入条件によっては抵抗体や電極
として使用できるため多層配線や３次元ＩＣにおいて有
効である。Furthermore, depending on the ion implantation conditions, the resistor can be used as a resistor or an electrode, which is effective in multilayer wiring and three-dimensional ICs.
第１図（Ａ）乃至第１図〈Ｆ）は本発明の半導体装置の
製造方法を説明する断面図、第２図（Ａ）乃至第２図（
Ｆ）は従来の半導体装置の製造方法を説明する断面図で
ある。
（１）は半導体基板、 （２）は第１の絶縁膜、 （３
）は第１の抵抗体、 （４）は第２の絶縁膜、 （５）
はホトレジスト膜、 （６）は第３の絶縁膜、 （７）
は第２の抵抗体、 （８）は第４の絶縁膜、 （９）は
ホトレジスト膜、 （１０）は第５の絶縁膜、（１１）
は電極である。FIG. 1(A) to FIG. 1(F) are cross-sectional views explaining the method of manufacturing a semiconductor device of the present invention, and FIG.
F) is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device. (1) is a semiconductor substrate, (2) is a first insulating film, (3
) is the first resistor, (4) is the second insulating film, (5)
is a photoresist film, (6) is a third insulating film, (7)
is the second resistor, (8) is the fourth insulating film, (9) is the photoresist film, (10) is the fifth insulating film, (11)
is an electrode.
Claims (1)
る工程と、この第１の絶縁膜上に第１の抵抗体を被覆す
る工程と、この第１の抵抗体上に第２の絶縁膜を被覆す
る工程と、この第２の絶縁膜上に所定形状のホトレジス
ト膜を形成する工程と、このホトレジスト膜を介して前
記第２の絶縁膜および第１の抵抗体を蝕刻して前記第１
の抵抗体をテーパーエッチングする工程と、前記ホトレ
ジスト膜を除去し第３の絶縁膜を前記半導体基板上に被
覆する工程と、この第３の絶縁膜上に第２の抵抗体を被
覆する工程と、この第２の抵抗体上に第４の絶縁膜を被
覆する工程と、この第４の絶縁膜上に所定形状のホトレ
ジスト膜を形成する工程と、このホトレジスト膜を介し
て前記第４の絶縁膜および第２の抵抗体を蝕刻して前記
第２の抵抗体を前記第１の抵抗体とは逆のテーパー形状
にエッチングする工程と、前記ホトレジスト膜を除去し
第５の絶縁膜を前記半導体基板上に被覆する工程と、前
記第１の抵抗体および前記第２の抵抗体と電気的に接続
される電極を形成する工程とを備えることを特徴とした
半導体装置の製造方法。(1) A process of coating a first insulating film on a semiconductor substrate of one conductivity type, a process of coating a first resistor on this first insulating film, and a process of coating a first resistor on this first resistor. a step of coating the second insulating film, a step of forming a photoresist film of a predetermined shape on the second insulating film, and etching the second insulating film and the first resistor through the photoresist film. The first
a step of tapering etching the resistor; a step of removing the photoresist film and covering the semiconductor substrate with a third insulating film; and a step of covering the third insulating film with a second resistor. , a step of coating this second resistor with a fourth insulating film, a step of forming a photoresist film of a predetermined shape on this fourth insulating film, and a step of coating the fourth insulating film through this photoresist film. etching the film and the second resistor so that the second resistor has a tapered shape opposite to that of the first resistor, and removing the photoresist film and replacing the fifth insulating film with the semiconductor. A method for manufacturing a semiconductor device, comprising the steps of: coating a substrate; and forming electrodes electrically connected to the first resistor and the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3615687A JPS63202955A (en) | 1987-02-19 | 1987-02-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3615687A JPS63202955A (en) | 1987-02-19 | 1987-02-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202955A true JPS63202955A (en) | 1988-08-22 |
Family
ID=12461911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3615687A Pending JPS63202955A (en) | 1987-02-19 | 1987-02-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202955A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019117858A (en) * | 2017-12-27 | 2019-07-18 | エイブリック株式会社 | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-02-19 JP JP3615687A patent/JPS63202955A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019117858A (en) * | 2017-12-27 | 2019-07-18 | エイブリック株式会社 | Semiconductor device and method of manufacturing the same |
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