JPS6320636U - - Google Patents

Info

Publication number
JPS6320636U
JPS6320636U JP11336386U JP11336386U JPS6320636U JP S6320636 U JPS6320636 U JP S6320636U JP 11336386 U JP11336386 U JP 11336386U JP 11336386 U JP11336386 U JP 11336386U JP S6320636 U JPS6320636 U JP S6320636U
Authority
JP
Japan
Prior art keywords
circuit
input signals
parallel
multiplexing
converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11336386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11336386U priority Critical patent/JPS6320636U/ja
Publication of JPS6320636U publication Critical patent/JPS6320636U/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第3図は本考案の一実施例を示す
構成図、第2図および第4図はタイミング発生部
から出力されるタイミング信号波形と入力信号波
形、出力信号波形、FF1〜FF4の出力信号波
形を示す波形図である。 TM1,TM2,TM3……タイミング発生部
、A1〜A8……論理積回路部、FF1〜FF4
……記憶回路部。
1 and 3 are block diagrams showing one embodiment of the present invention, and FIGS. 2 and 4 show the timing signal waveform output from the timing generator, the input signal waveform, the output signal waveform, and FF1 to FF4. FIG. 3 is a waveform diagram showing an output signal waveform. TM1, TM2, TM3...timing generation section, A1-A8...AND circuit section, FF1-FF4
...Memory circuit section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デジタル回路で構成した並直列変換用シフトレ
ジスタにおいて並列入力信号を時分割多重変換す
るためのタイミング信号発生部並びに該入力信号
を直列出力信号に変換するための論理積ゲート回
路および論理和回路から構成されることを特徴と
する多重化回路。
A shift register for parallel-to-serial conversion configured with a digital circuit consists of a timing signal generation section for time-division multiplexing of parallel input signals, and an AND gate circuit and an OR circuit for converting the input signals into serial output signals. A multiplexing circuit characterized in that:
JP11336386U 1986-07-25 1986-07-25 Pending JPS6320636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11336386U JPS6320636U (en) 1986-07-25 1986-07-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11336386U JPS6320636U (en) 1986-07-25 1986-07-25

Publications (1)

Publication Number Publication Date
JPS6320636U true JPS6320636U (en) 1988-02-10

Family

ID=30995097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11336386U Pending JPS6320636U (en) 1986-07-25 1986-07-25

Country Status (1)

Country Link
JP (1) JPS6320636U (en)

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