JPS63209097A - Semiconductor nonvolatile ram - Google Patents

Abstract

PURPOSE:To obtain the semiconductor nonvolatile RAM of a low power consumption and of a low price by constituting it by connecting a nonvolatile MOS capacitor to a volatile RAM through a selection transistor. CONSTITUTION:An N<+> region 2, which is the output terminal Q of the volatile RAM, that two invertors are connected in series, and is the source region of a selection gate transistor (TR) T1, is formed on the surface of a P-type semiconductor substrate 1, and the selection gate TR T1, consisting of a selection gate insulation film 3 and a selection gate electrode 5, is connected in series, and further, the nonvolatile MOS capacitor C, consisting of a gate insulation film 4, a floating gate electrode 6, a control gate electrode 8 and an erasing terminal 10, is connected in series. Thus, because the power consumption at the time of a storing and a recall is small, and a structure is simple, the nonvolatile RAM of a low price and a low power consumption can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile RAM (random access memory) used in electronic equipment such as computers.

[Summary of the invention]

The present invention relates to a semiconductor non-volatile RAM that combines volatile memory and non-volatile MOS (Metal-Oxide).
-3cmiconductor) capacitor, it is a low-power and inexpensive semiconductor non-volatile RA.
This is what made M possible.

[Conventional technology]

Conventionally, as shown in FIG. 2, eight transistors are connected to the output terminal of a static RAM with an inverter connected in series. and non-volatile MO3) transistor T3. It has a configuration in which transistors B T a are connected in series. (IE
EE Journal of 5solid-3tate
Circuits, vol, 5c-18, No5,
0CTOBER1983pp525-532) [Problems to be solved by the invention] However, the conventional semiconductor non-volatile RAM requires three transistors in addition to the static RAM, and furthermore, the information of the non-volatile MOS transistors must be transferred to the static RAM. The disadvantage is that sometimes large direct currents are required.

Therefore, in order to solve these conventional drawbacks, the present invention aims to provide a low-power, inexpensive semiconductor nonvolatile RAM.

[Means for solving problems]

In order to solve the above problems, this invention provides volatile RAM
Additionally, a nonvolatile MOS capacitor is connected via a selection transistor, making it possible to create a low-power, inexpensive semiconductor nonvolatile RAM.

[Effect]

The semiconductor non-volatile RAM configured as described above has a single H structure, and furthermore, it is a low-power and inexpensive semiconductor because it does not require direct current when transferring information from the non-volatile MOS capacitor to the volatile RAM. Non-volatile RAM can be realized.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In Figure 1, a selection gate transistor T is connected to the output terminal Q of a volatile RAM in which two inverters are connected in series.
A nonvolatile MOS capacitor C is provided via +.

In the case of FIG. 1, the volatile RAM is a static RAM, but the volatile RAM is a dynamic RAM.
The present invention can also be implemented with M.

Volatile RAM output terminal and selection gate transistor T,
A cross-sectional view of a nonvolatile MOS capacitor C is shown in FIG. 3, a P-type semiconductor substrate! An N'' region 2, which is the output terminal Q of the volatile RAM and the source region of the select gate transistor, is formed on the surface of the N'' neck region 2, and a select gate insulating film 3 and a select gate electrode are formed in series with the N'' neck region 2. 5, and a nonvolatile MOS capacitor C consisting of a gate insulating film 4, a floating gate electrode 6, a control gate electrode 8, and an erase terminal 10 is further connected in series.

The operation of nonvolatile RAM will be explained.

First, if the selection gate transistor T1 is turned off, the nonvolatile RAM of the present invention can operate as a normal RAM (random access memory) because it is not affected by the nonvolatile MOS capacitor C. .

Next, the so-called store operation in which the information in the RAM is transferred to the nonvolatile MOS capacitor C is performed as follows. First, when a high voltage is applied to the erase terminal 10 with respect to the control gate electrode 8, the floating gate electrode 6 and the erase A high electric field is applied to the erase tunnel insulating film 9 between the electrodes IO, and as a result of a tunnel current flowing, the potential of the floating gate electrode 6 is charged to the positive side.Next, a power supply voltage is applied to the selection gate electrode 5, When a high voltage is applied to the control gate electrode 8 with respect to the substrate l, R
When the output terminal 2 of the AM is at the power supply voltage level, the selection gate transistor T1 is turned off, so the potential of the floating gate electrode 6 remains positively charged. Conversely, when the output terminal 2 of the RAM is at a lower level than the potential of the substrate 1, the selection gate transistor T is sufficiently turned on, so that the potential of the substrate surface under the floating gate electrode 6 is lower than that of the RAM. The potential becomes equal to the potential of the output terminal 2, and a high electric field is applied to the gate insulating film 4 between the floating gate electrode 6 and the substrate 1. As a result, a tunnel current flows through the gate insulating film 4, and the floating gate electrode 6 is negatively charged. That is, R.A.
If the output terminal 2 of M is on the power supply voltage side, the floating gate electrode 6
is charged to the positive side, and when the output terminal 2 is at a low potential of the substrate 1, the floating gate electrode 6 is charged to the negative side.

If the floating gate electrode 6 is positively charged, a large amount of charge can be accumulated on the surface of the substrate 1 under the floating gate electrode 6 because the area under the floating gate electrode 6 is strongly inverted.

In other words, this is equivalent to connecting a large capacitor to the selection gate transistor T1. This capacitor is the capacitance value between the substrate surface and the substrate and between the control gate electrode. When the floating gate electrode 6 is negatively charged, the surface of the substrate 1 under the floating gate electrode 6 cannot accumulate M charges, so this is equivalent to not connecting anything to the selection gate transistor T1. Become.

As explained above, when the output terminal 2 of the RAM is at a high potential due to the store operation, the selection gate transistor T
A capacitor with a large capacitance is connected through I, and conversely, when the output terminal 2 of the RAM is at a low potential (substrate 1 side), a capacitor with a small capacitance is connected through the selection gate transistor T1. The capacitor connected to this selection gate transistor T can change its capacity and store it according to the information in the RAM, and is non-volatile. Therefore, this substrate 1, gate insulating film 4, and floating gate electrode 6
A capacitor consisting of the control gate electrode 8 and the erase electrode lO becomes a nonvolatile MOS capacitor C.

Next, the so-called recall operation that transfers the information of the nonvolatile MOS capacitor C to the RAM is as follows.If the 0 selection gate transistor T1 is turned on and a large capacitor is connected to the output terminal 2, the output The RAM is designed so that the potential of the output terminal is at the same low level as the substrate 1 when the potential of the terminal is at the level of the power supply voltage and a small capacitor is connected. With this design, information on the nonvolatile MOS capacitor can be recalled to the RAM. At the time of recall, since the nonvolatile MOS capacitor C is connected to the selection gate transistor TI, no direct current flows.

In other words, recall can be performed with low power consumption.

〔Effect of the invention〕

As explained above, this invention has a structure in which a semiconductor non-volatile MoS capacitor is connected to a RAM via a selection gate transistor, so power consumption during storage and recall is small, and the structure is simple! To be simple,
It is possible to realize an inexpensive nonvolatile RAM with low power consumption. The structure of the nonvolatile MOS capacitor used to explain the present invention is as follows:
It does not have to be a floating gate type, but an MNOS type (IE [iE
Journal of 5 solid-State C1
rcuits, vol, 5c-15+ No3. J.U.
NE1980 pp346-353).

Further, the operation is the same even if the control gate electrode and the erase electrode are provided in the substrate instead of on the floating gate electrode.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor non-volatile RAM according to the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor non-volatile RAM. FIG. 3 is a cross-sectional view of the nonvolatile MOS capacitor of the present invention. 1... Semiconductor substrate 2... RAM output terminal 5... Selection gate electrode 6... Floating gate electrode 8... Control gate electrode 10... Erasing electrode and above Applicant: Seiko Electronics Co., Ltd. Hand of the Invention "Ff tree 1 Brushless RAM circuit port Figure 1 Figure 2 Lower 4'F TiMOS key - side view Figure 3

Claims (2)

[Claims] (1) A semiconductor nonvolatile RAM characterized in that a nonvolatile MOS capacitor is connected in series to an output terminal of a semiconductor volatile memory via a selection transistor. (2) The nonvolatile MOS capacitor includes a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, and a charge storage layer provided in the gate insulating film. 2. The semiconductor nonvolatile RAM according to claim 1, characterized in that: