JPS63211024A - data processor - Google Patents

Abstract

PURPOSE:To speed up multiplier operation by generating an input signal of an arithmetic operation unit through a selector which transmits a multiplicand, a complement, or zero selectively and a shifter which receives the output signal of the arithmetic operation unit in parallel. CONSTITUTION:The multiplicand is inputted to a register 1, which is supplied to a complement device 3 to generate the complement, and the multiplicand, complement, or data zero is supplied selectively to one input of the arithmetic operation unit 4 through the selector 3. The output signal of the arithmetic operation unit 4 is supplied to the other input of the arithmetic operation unit 4 in parallel through a shifter A5 and a shifter C7. A multiplier, on the other hand, is inputted to a shifter B6 and a signal consisting of plural bits required for unit arithmetic is supplied to a canonical recorder 2 through a code extending circuit 8 to generate control signals for the selector 3 and shifters A5 and C7, thereby performing partial product arithmetic corresponding to the plural bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processor, and relates to a technique that is effective for use in, for example, a microprocessor having a multiplication function.

[Conventional technology]

Multiplication in microprocessors is performed from combinations of additions. Regarding such multiplication methods, for example, see CQ Publishing Co., September 15, 1980, Internal Structure and Machine Language of a Micro Combiator, J. Kunio Fukunaga, p. 147.
~ pages 150. This multiplication has the problem that when the multiplier and multiplicand are 8 bits, the calculation operation is slow because eight repeated addition operations are required. Therefore,
A multiplication method using a uniform digit shift method using multiple bits, such as 2-bit or 3-bit multiplier, has been proposed (for example, Computer System Viewed from Patent R, published by Japan Institute of Invention and Innovation, April 10, 1980, p. 1). 336), this-
In the bridge girder movement method, for example, the multiplier is uniformly set to 2 starting from the lowest digit.
Bits are grouped one by one, and partial products of 0 to 3 times the multiplicand are sequentially added to three bits with adjacent lower digits. Therefore, if the multiplier and multiplicand are 8 bits, multiplication can be performed by four addition operations.

[Problem that the invention seeks to solve]

However, in such a bridge girder movement method,
The circuit that forms the above partial products becomes complex, and the number of digits increases according to the above partial products. Therefore, even if the multiplicand and multiplier are 8 bits, an arithmetic unit with a 9-bit input is required to perform sequential addition. becomes necessary.

An object of the present invention is to provide a data processor that achieves high-speed multiplication operations with a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

(Means for Solving the Problems) A brief overview of typical inventions disclosed in this application is as follows.

That is, the complement of the multiplicand is formed by a complementer, and the complement is transmitted to one input of the arithmetic operation unit via a selector that selectively transmits the multiplicand, its complement, or zero;
The other input of this arithmetic operation unit is transmitted through a first shifter and a third shifter that receive the output signal in parallel, and a multiplier is transmitted to the second shifter to encode the multi-bit signal necessary for the unit operation. The signal is supplied to the canonical recorder via an expansion circuit to form control signals for the selector and the first and third shifters, thereby executing a partial product operation corresponding to a plurality of bits.

[For production]

According to the above-mentioned means, since the input signal of the military arithmetic operation unit is formed via the selector or shifter, high-speed multiplication operation can be realized using the arithmetic operation unit corresponding to the data length of the multiplicand and the multiplier.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of an arithmetic and logic operation unit to which the present invention is applied. Although not particularly limited, each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, although not particularly limited, the multiplicand and the multiplier are 8 pinto data. The multiplicand is taken into register 1. The output signal of this register 1 is fed to a complementer, where a complement is formed. This complement, the multiplier and data 0 are selectively supplied to one input of the arithmetic operation unit (ALtJ) 4 by a selector. In the figure, the complementer and selector are shown by one circuit block 3.

The output signal of the arithmetic operation unit 4 is connected to the first
is supplied to shifter A5. The output signal of this shifter A5 is supplied in parallel to a third shifter C7, and the output signal of the arithmetic operation unit 4 is supplied to the other input via these shifters A5 and C7. Also,
The multiplier is taken into the second shifter B6. The selector and each shifter A to C are composed of 8 bits.

The multiplier taken into the shifter B6 is the least significant bit L
A total of 3 bits each including 2 bits from the SB and the adjacent upper 1 bit are supplied to the sign extension circuit 8. That is, as will be described later, the first time is a combination of 3 bits from 0 to 2, the second time is a combination of 3 bits from 2 to 4, and so on. 3 from this sign extension circuit 8
The bit signals BO to B2 are supplied to a canonical recorder 2. The standard recorder 2 carries the signals BO to B2 and the carry output Cout of the previous cycle.
received as in, data X1. Form the X2 and - times signals.

The canonical recorder 2 forms control signals for the shifter A5, shifter C7 and selector according to the information bits of the output signals XI, X2 and -.
indicates the multiplicand, its complement, or data 0 to be alternatively transmitted to the selector. Also, canonical recorder 2
instructs shifter A5 to perform a 1-bit or 2-bit right shift operation, and instructs shifter C7 to perform a through or 1-bit right shift operation.

Table 1 The multiplication operation of this embodiment circuit will now be explained with reference to the operation diagram shown in FIG.

In the first addition operation, of the multiplier supplied to the shifter B6, three bits starting from the least significant bit SB are supplied in parallel to the sign extension circuit 8. Along with this output operation, in the second addition operation of the 0th order, which is shifted to the right by 2 bits, the lower 3 bits of the signal are changed to 3 bits 2 to 4 by the 2-bit right shifting operation of shifter B. It is considered to be a signal. Similarly, in the third addition operation, a 3-bit signal of 4 to 6 is used.
In the fourth addition operation, the signal is a 3-bit signal of 6 to 8. However, this 4th B! In the second operation cycle, since the multiplier consists of 8 bits from 0 to 7, bit 8 is added by the sign extension circuit. Note that when the data length is large, such as 16 bits, the above-mentioned signals BO to B2 are formed by the same combination as above.

The converted signal X2 of the canonical recorder 2 is generated by the output signals BO to B2 of the sign extension circuit 8 in each of the above operation cycles.
．． If XI and - times are 000, addition of 10 is performed, that is, the selector outputs data O. Shift shifter A5 2 bits to the right. Shifter C7 passes the signal through. That is, in the first addition operation, data O is taken into shifter A as is. In the second and subsequent addition operations, the signal of shifter A is only shifted two bits to the right.

Further, the conversion signal X2. If XI and - times are 010,
Addition of the multiplicands is performed, ie the selector supplies the multiplicands to one input of the arithmetic unit. The addition result from the previous operation cycle held in shifter A5 is transferred to shifter C
is supplied to the other input of the arithmetic unit 4 via
The addition is performed and taken into shifter A5. The result of this operation is shifted to the right by 2 bits. Note that in the case of the first addition operation, the multiplicand is taken into shifter A as it is.

Further, the conversion signal X2. If Xl and - times 100,
The multiplicand is added by ×2, ie, the selector supplies the multiplicand to one input of the arithmetic unit. The addition result in the previous operation cycle held in shifter A5 is
It is shifted to the right by one bit via shifter C and supplied to the other input of arithmetic operation unit 4. As a result of this shift operation, the 1-bit signal that has protruded from the least significant bit of shifter C7 is taken into the most significant bit of shifter B.

As a result of shifting the previous addition result to the right by 1 bit as described above, the above multiplicand is doubled (1
The result of the addition of both is taken into shifter A. At this time, shifter A is
A 1-bit right shift is performed and the signal is supplied from the most significant bit of the shifter B. As a result, the upper two bits of shifter B are supplied with a 1-bit signal from shifter C and a 1-bit signal from shifter A. In the case of the first addition operation, the multiplicand is taken into shifter A as it is, 0 from shifter C7 is added to its least significant bit, and it is shifted one bit to the right.

As a result, data obtained by doubling the multiplicand with respect to the second most significant bit of shifter B is taken into the most significant bit of shifter A and shifter B.

Further, the conversion signal X2. If XI and - times are 011, then
This addition operation in which the -1 times multiplicand is added is such that the selector selects and outputs the complement instead of the multiplicand, and is similar to the addition of the + multiplicand described above.

Further, the conversion signal X2. If XI and - times are 101, then
The multiplicand multiplicand x2 is subtracted, or if you want to add -(multiplicand multiplicand x2), that is, the selector supplies the complement to one input of the arithmetic unit in place of the multiplicand. The addition result from the previous operation cycle held in shifter A5 is shifted rightward by one bit via shifter C and supplied to the other input of arithmetic operation unit 4. As a result of this shift operation, the 1-bit signal that has protruded from the least significant bit of shifter C7 is taken into the most significant bit of shifter B. As a result of the previous addition result being shifted to the right by 1 bit as described above, from the perspective of the previous addition result, it becomes the same as if the above complement was doubled (carry by 1 bit), and the addition result of both is It is taken into shifter A. At this time, shifter A performs a 1-bit right shift and supplies the most significant bit of shifter B. As a result, the upper two bits of shifter B include one bit from shifter C and shifter A.
A 1-bit signal from is supplied. In addition, in the first addition operation, the complement number is taken into shifter A as it is, and 0 from shifter C7 is added to the least significant bit.
It is shifted one bit to the right. by this,
With respect to the complement, the second most significant bit of shifter B is taken as a reference, and data doubled is taken into the most significant bit of shifter A and shifter B.

By using the five types of addition operations as described above, it is possible to perform a multiplication operation using a uniform digit shift method of 2 bits at a time. That is, partial products of 2 bits, that is, 0 to 3 times the multiplicand, are sequentially added and the digits are shifted 2 bits at a time. Then, by referring to the signal of the upper 1 bit added to the above 2 bits, and performing the code conversion as described above, 3 times is processed as 4 times - 1 times. That is, in that step, processing is performed by 11 times, and in the next step, processing is performed by 4 times (2-bit shift operation). Similarly, 2 times is also processed by 4 times - 2 times. By doing so, the multiplication of the 8-bit multiplier and the multiplicand can be realized in four operation cycles.

Furthermore, the arithmetic operation unit 2 is supplied with the multiplicand or its complement, or data 0, and a shifter is provided on the output side of the arithmetic operation unit to supply the other input. A signal with a data length of 8 bits can always be supplied to the arithmetic unit.

In addition, it is possible to supply the other addition data to the arithmetic operation unit by shifting or passing the operation result of shifter A through shifter C, and when adding the multiplicand of ±2 times as described above, the shifter C's 1 The 1-bit signal protruding from the bit shifting operation is supplied as it is to the shifter B as the least significant bit of the addition result, thereby simplifying the data transmission path and thereby further increasing the speed.

In addition, by adding the above sign extension circuit, there is almost no distinction between signed numbers (2's complement) and signed innumerable numbers (absolute value display numbers), that is, signed infinity is treated as a positive signed number. By handling, multiplication as described above can be performed.

The effects obtained from the above examples are as follows. That is, (1) A complement of the multiplicand is formed by a complementer, and the multiplicand, its complement, or zero is transmitted to one input of the arithmetic operation unit via a selector that selectively transmits the multiplicand, its complement, or zero; The output signal is transmitted through a first shifter A and a third shifter C that receive the output signal in parallel to the other input of The selector, shifter A, Since the input signal of the arithmetic operation unit is formed through C, it is possible to realize a high-speed multiplication operation using a uniform digit shift method using an arithmetic operation unit that corresponds to the data length of the multiplicand and the multiplier.

(2) When performing an addition operation of ±2 times, the data propagation path can be shortened by shifting the shifter C by 1 bit and using the protruding least significant bit as the addition result. Thereby, the above-mentioned (1) can be combined to further speed up the operation.

(3) The effect that multiplication can be performed without distinguishing between signed innumerables and signed numbers by supplying the multi-bit unit signal necessary for the arithmetic operation from the shifter that receives the multiplier to the sign extension circuit. is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, as shown in FIG. 3, a multiplier is set in the register 10, its output is supplied to a shifter D9, the output of this shift D9 is supplied on one side to the canonical recorder 2, and on the other hand the above-mentioned register! The multipliers are sequentially shifted by the loop of the multiplier register 10 and the shifter D9, which may be supplied to the multiplier D9. However, the shifter D9 is an arithmetic shifter when a signed number is multiplied, that is, the shift input is the most significant bit MSB, and a logical shifter when a signed number is multiplied.
In other words, the shift input is set to O. Other configurations and operations are as follows:
This is similar to the embodiment shown in FIG. 1 above.

The multiplicand and the multiplier may be composed of 16 bits or the like. In this case, the bit length of the arithmetic operation unit and shifter is set in accordance with the above data length. Further, in place of the shifter B, another shifter connected in series to the shifter A may be provided.

The present invention can be widely used as a data processor that causes the arithmetic unit to perform multiplication.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the complement of the multiplicand is formed by a complementer, and is transmitted to one input of the arithmetic operation unit via a selector that selectively transmits the multiplicand, its complement, or zero, and the other input of the arithmetic operation unit is The output signal is transmitted to the input through shifters A and C which receive the output signal in parallel, and the multiplier is transmitted by shifter B to the canonical recorder via a sign extension circuit to supply a multi-bit signal necessary for the unit operation. The above selector and shifter A.

By forming a control signal of C to execute a partial product operation corresponding to a plurality of bits, a high-speed multiplication operation using a uniform digit shift method can be realized using an arithmetic operation unit corresponding to the data length of the multiplicand and the multiplier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a diagram for explaining the partial product addition operation. FIG. 3 is a block diagram showing another embodiment of this invention. It is. 1...Register (multiplicand), 2...Canonical recorder, 3...
・Complementer & selector, 4... Arithmetic operation unit, 5...
Shifter A, 6...Shifter B, 7...Shifter C18...Sign extension circuit, 9...Shifter D110...Register (multiplier) Fig. 1 Fig. 2 Fig. 5B 1---+1--H1 month)--e 2-2-',-'I' Fig. 3

Claims (1)

[Claims] 1. A complementer that receives a multiplicand, a selector that transmits the multiplicand, its complement, or zero, an arithmetic operation unit to which an output signal of the selector is supplied to one input, and this arithmetic operation unit. a first shifter receiving the output signal of the first shifter; a third shifter receiving the output signal of the first shifter and transmitting the signal to the input of the other of the arithmetic operation units; a second shifter receiving the multiplier; a sign extension circuit that receives a multi-bit signal necessary for unit calculation from the second shifter; and a sign extension circuit that receives the output signal of the sign extension circuit and forms control signals for the selector and the first and third shifters. A data processor comprising: a canonical recorder that executes partial product operations corresponding to a plurality of bits. 2. The signal from the least significant bit of the first shifter is serially transmitted to the most significant bit of the second shifter according to the shift operation, and a multiplication result is obtained from the first and second shifters. A data processor according to claim 1.