JPS6321394B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit, and more particularly, to provide a noise reduction circuit that can significantly reduce noise contained in a luminance signal reproduced from a magnetic recording medium with a simple circuit configuration. With the goal.

2. Description of the Related Art Conventionally, noise reduction circuits have been known for reducing noise caused by recording and reproduction included in video signals reproduced from magnetic recording media in magnetic recording and reproduction apparatuses and the like. FIG. 1 shows a block system diagram of an example of a conventional noise reduction circuit. In the figure, the reproduced luminance signal containing noise that has entered the input terminal 1 is processed by the 1H delay circuit 2.
Delayed by horizontal scanning period (1H). The subtracter 3 subtracts the reproduced luminance signal delayed by 1H by the 1H delay circuit 2 from the reproduced luminance signal from the input terminal 1.
Here, since the video information of the 1H time interval of the reproduced luminance signal is extremely similar, the subtracter 3 extracts noise that is not related to the video information. This noise is passed through limiter 4 to attenuator 5.
is supplied to the subtractor 6 after being level attenuated here.
is supplied to The subtracter 6 subtracts the noise from the attenuator 5 from the reproduced luminance signal input to the input terminal 1, and outputs the reproduced luminance signal with reduced noise to the output terminal 7. However, this conventional noise reduction circuit has a noise reduction of about 3 dB at most.
It was only possible to improve the signal-to-noise ratio.

In addition, as other conventional noise reduction circuits, video signals have extremely strong autocorrelation between frames, while noise contained in video signals has almost no autocorrelation. Therefore, there was a noise reduction circuit that lowers only the noise energy while the energy of the video signal hardly changes on average for each frame period, but this circuit requires a frame memory, its control device, and other circuits. The drawbacks were that the circuit was large, complex, and expensive.

The present invention eliminates the above drawbacks, and the second
One embodiment will be described with reference to the drawings below.

FIG. 2 shows a block system diagram of an embodiment of the noise reduction circuit according to the present invention. In the figure, a reproduced luminance signal containing noise, which is frequency-modulated and recorded on a magnetic recording medium, reproduced from the frequency-modulated signal, and extracted through an FM demodulator, enters an input terminal 8 and is supplied to a subtracter 9. 1H, which will be described later here.
By subtracting the reproduced luminance signal from the delay circuit 10, noise not related to line correlation is mainly extracted. Now, the reproduced luminance signal from the input terminal 8 has the waveform shown in Figure 3A, and the peak value is
1V, and the reproduced luminance signal from the 1H delay circuit 10 has the waveform shown in Figure B, and the peak value is
Assuming that the voltage is 1V, the output signal waveform of the subtracter 9 will be as shown in FIG. The output signal of the subtracter 9 is amplitude-limited by a limiter 11, and a signal within the range of about 0.1V to 0.2V from the signal waveform shown in FIG. 3C, for example, is extracted. Therefore, limiter 11
A signal as shown in FIG. The subtracter 13 subtracts the signal from the attenuator 12 from the reproduced luminance signal from the input terminal 8 and outputs the reproduced luminance signal with reduced noise to the output terminal 14, while being supplied to the 1H delay circuit 10. Thereafter, the same operation as above is repeated.

As described above, according to this embodiment, by configuring a closed loop that feeds back the reproduced luminance signal output to the output terminal 14 to the 1H delay circuit 10, the attenuation coefficient (gain) of the attenuator 12 can be adjusted as described later. Accordingly, it is possible to significantly improve the SN ratio.

Next, regarding the SN ratio improvement operation by the circuit of the present invention,
A more detailed explanation will be given based on this embodiment. Now, let S _k+1 be the input reproduced luminance signal of the input terminal 8, let n _k+1 be the noise contained therein, and let S k be the reproduced luminance signal 1H before taken out from the 1H delay circuit 10 at this point, and let S _k be the noise contained therein. Assuming that the noise to be generated is n _x (k), the subtracter 9 extracts a signal expressed as (S _k+1 −S _k )+(n _k+1 −n _x (k)). This signal is limiter 1
1 to the attenuator 12, where the signal is multiplied by a gain A and level attenuation is performed. Therefore, from the attenuator 12, A(S _k+1 −S _k )+A(n _k+1 −n _x (k))
A signal expressed by the formula is extracted. Thereby, the output signal of the subtracter 13 can be expressed by the following formula: {(1-A)S _k+1 +AS _k } +{(1-A)n _k-1 +An _x (k)}. Here, since the amplitude of the portion of the input signal without line correlation is limited by the limiter 11, it can be considered that S _k =S _k+1 =S, so the above equation becomes S+{(1-A)n _{k- 1} + An _x (k)}. The output reproduced luminance signal expressed by this formula is
Since it is fed back to the 1H delay circuit 10, the above equation becomes S+
It can be expressed as n _x ^(k+1) . Noise n _x ^(k+1) is n _x ^(k+1) = (1-A)・n _k+1 +A・n _x (k)=(1-A)・
n _k+1 +A {(1-A)・n _k +A・n _x ^(k-1) }=(1-A)・n _k+1 +A(1-A)
・n _k +A ² {(1-A)n _k-1 +A・n _x ^(k-2) }=(1-A){n _k+1 +An _k +A ² n _k-1 +
…}(1).

In equation (1), the noise at 1H intervals n _k+1 , n _k ,
Assume that the individual energies of n _k-1 ,... are equal,
And, assuming that its absolute value is N, the energy of n _x (k) is expressed by the following equation.

Therefore, the noise improvement degree n _x (k)/N is obtained from equation (2). becomes.

FIG. 4 is a characteristic diagram showing the degree of improvement of the SN ratio by the circuit of the present invention, where the horizontal axis is the gain A of the attenuator 12, and the vertical axis is the gain A of the attenuator 12.
The degree of SN ratio improvement is shown in dB based on equation (3). As is clear from FIG. 4, as the gain A approaches 1, an extremely large degree of improvement in the SN ratio can be obtained. Therefore,
As a noise reduction circuit, the above gain A
It is better to make the gain A as close to 1 as possible because the noise reduction effect is greater, but in reality, if the value of the gain A is too close to 1, the influence from the previous line will be large and the reproduced image will become blurry, and the noise will be reduced. Among them, only the components with line correlation are emphasized, which causes the side effect that vertical trailing noise as if it is raining stands out in the playback screen, so the gain A is 0.5.
~0.7 is optimal. When the gain A is about 0.5 to 0.7, the SN ratio is about 5 to 0.7, as shown in Figure 4.
The improvement is about 8 dB, which is much larger than the conventional noise reduction circuit shown in FIG. Moreover, according to the circuit of the present invention, the circuit configuration can be simpler and cheaper than a noise reduction circuit using a frame memory.

In addition, if the limiter 11 is applied too much, noise will be cut out, while if the limiter is applied only a little, the influence of parts with no line correlation in the signal will appear on subsequent lines, causing the reproduced image to blur. In severe cases, synchronization may be lost. Therefore, in order to prevent these phenomena, it is desirable to set the limiter level to about 0.1 to 0.2, assuming that the peak value of the input signal to the limiter 11 is 1.

FIG. 5 shows a specific circuit diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 2 are given the same numbers. The subtracter 9 consists of a PNP transistor Tr ₁ , and extracts the output signal of the 1H delay circuit 10 supplied to the base of the transistor Tr ₁ from the collector of the transistor Tr ₁ in reverse phase and adds it to the reproduced luminance signal from the input terminal 8 . It is configured to do this. 1H delay circuit 10 is an NPN transistor
The output reproduced luminance signal from the collector of Tr ₅ is supplied to the balanced modulator 16 in the IC 15, and the crystal oscillator 20,
The signal from the crystal oscillation circuit 17 consisting of NPN transistor Tr ₃ etc. is balanced modulated and converted into the transmission band of the 1H delay line 18, and this is converted into the transmission band of the NPN transistor Tr3.
After impedance conversion with Tr ₂ , 1H delay line 1
The signal is supplied to the balanced modulator 19 through the channel 8, where it is converted to the original band and then supplied to the base of the transistor _Tr1 .

The limiter 11 includes an amplifier 21, a diode and
Consists of NPN transistor Tr ₄ , etc. Further, VR is a variable resistor that constitutes the attenuator 12 and the subtracter 13, and the output signal from its slider is passed through the base and emitter of the NPN transistor Tr ₆ to the output terminal 14.
It is also supplied to the base of transistor _Tr5 .

Note that the circuit of the present invention does not use a filter circuit to extract the noise in the input video signal, so a high-frequency filter is used to extract the noise, and the output is passed through a limiter and then reversed in phase. Compared to conventional circuits such as noise suppression circuits and non-linear emphasis that overlap the input video signal, it is effective in reducing noise at the boundary between black and white (edges), and can be used in conjunction with the conventional circuits mentioned above. This allows for more effective noise reduction.

As described above, the noise reduction circuit according to the present invention includes a delay circuit that gives an input signal a delay time of one horizontal scanning period, and a second circuit that subtracts the input video signal containing noise from the output signal of the delay circuit. 1
a subtracter, a limiter that limits the amplitude of the output signal of the first subtracter, an attenuator that attenuates the output signal level of the limiter, and subtracts the output signal of the attenuator from the input video signal. and a second subtracter that feeds back the video signal obtained by the delay circuit to the delay circuit, so that the video signal whose noise is significantly reduced compared to the conventional noise reduction circuit using the delay circuit is input to the delay circuit. 2, and the circuit configuration is simpler and cheaper than the conventional circuit that performs noise reduction through digital processing using frame memory.
In particular, since the limiter is configured to output a signal with a peak value of 0.1 to 0.2 when the peak value of the input signal is 1, it is possible to reproduce the signal portion without line correlation without cutting out noise. In addition, since the gain of the attenuator is set to 0.5 to 0.7, it is possible to reduce the negative influence on the playback screen and at the same time obtain a large degree of improvement in the SN ratio. Since it is effective in reducing noise at this boundary area, it has many features such as being able to perform even more suitable noise reduction when used in conjunction with conventional circuits that have been unable to reduce noise at this boundary area.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of a conventional noise reduction circuit, FIG. 2 is a block system diagram showing an embodiment of the noise reduction circuit according to the present invention, and FIGS. Figure 4 is a signal waveform diagram for explaining the operation; Figure 4 is a characteristic diagram showing the relationship between the gain of the attenuator and the degree of improvement of the SN ratio in the circuit of the present invention;
FIG. 5 is a specific circuit diagram showing an embodiment of the noise reduction circuit according to the present invention. 1, 8...Reproduction brightness signal input terminal, 2, 10...
...1H delay circuit, 3, 6, 9, 13...subtractor,
4, 11... limiter, 5, 12... attenuator,
7, 14...Reproduction brightness signal output terminal, 18...
1H delay line.

Claims (1)

[Scope of Claims] 1. A delay circuit that provides a delay time of one horizontal scanning period to an input signal; a first subtracter that subtracts an input video signal containing noise from an output signal of the delay circuit; a limiter that limits the amplitude of the output signal of the first subtracter; an attenuator that attenuates the output signal level of the limiter; and an image obtained by subtracting the output signal of the attenuator and the input video signal. A noise reduction circuit comprising a second subtracter that feeds back a signal to the delay circuit, and extracts an input video signal with reduced noise from the second subtracter. 2. The noise limiter according to claim 1, wherein the limiter level is set to output a signal with a peak value of 0.1 to 0.2 when the peak value of the input video signal is 1. reduction circuit. 3. The noise reduction circuit according to claim 1 or 2, wherein the attenuator has a gain of 0.5 to 0.7.