JPS632165A - Signal processing circuit for cd reproducing device - Google Patents

Abstract

PURPOSE:To remarkably decrease the number of components by providing 1st-4th counters operated differently respectively so as to eliminate the need for an arithmetic circuit. CONSTITUTION:The 1st counter designates a write address, the 2nd counter 3 designates a read address so as to increase the write address more than the read address by, e.g., 6 areas. After the count of the 2nd counter 3 is preset in the 3rd counter 6, when a clock pulse COMPCL is applied to the 3rd counter 6 to start counting and a disk is rotated normally, the coincidence between the 1st counter 1 and the 3rd counter 6 is detected by using 6 clock pulses COMPCL. A control circuit increases/decreases the frequency division ratio of a frequency divider circuit of a servo circuit by using the count of the 4th counter and a prescribed value is preset to the 1st counter at the outside of a prescribed range.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a signal processing circuit for a CD (compact disc) playback device, and in particular to a signal processing circuit for storing symbol data read from a CD in a RAM. ↑ Read out and deinterleave the provided symbol data and store it in RAM.
The present invention relates to a signal processing circuit that controls the rotational speed of a disk motor based on the amount of data stored in the disk motor.

(b) Conventional technology In the CD system, an error correction method called CIRC (cross-interleaved Reed-Solomon code) is used, and 24 information symbols (8 bits) are created by 6 samples each of the right channel and the left channel. and 8 parity symbols (8 bits), for a total of 32 symbols. An 8-bit subcode is attached to these 32 symbols, and these are EFM-modulated and recorded on the disk as one frame together with a 24-bit frame synchronization signal. Recording on the disk is performed using the constant linear velocity (CLV) method.

The signal processing circuit in the CD playback device decodes the EFM signal read from the disc to create 8-pit symbols, sequentially stores the symbols in RAM, and reads out the symbols stored in RAM. The CIRC circuit performs CI error correction and C2 error correction for each frame, and the corrected symbols are stored in the RAM again, and the corrected symbols are read out from the RAM and applied to the DA conversion circuit. Is going.

In addition, in the CLV system, the disk motor is controlled by a servo circuit so that the linear velocity of the disk is constant. That is, the phases of a signal obtained by dividing a synchronizing signal created by a PLL circuit based on an EFM signal by a frequency dividing circuit and a signal obtained by dividing a reference signal from a reference oscillator by a frequency dividing circuit are compared, and these signals are determined to be - The disc motor is controlled to match the

However, if the servo of the disk motor becomes inaccurate due to a dropout of the EFM signal, the linear velocity of the disk will no longer be constant, and jitter will occur in the EFM signal. These jitters can be absorbed by the RAM within a certain range, but beyond that range, the jitters cannot be absorbed.

Therefore, in the past, the amount of data accumulated in the RAM was detected, and the frequency division ratio of the frequency divider circuit that divided the frequency of the synchronization signal created based on the EFM signal was increased or decreased depending on the amount of accumulation, or the reference signal was divided. By increasing or decreasing the dividing ratio of the frequency divider circuit,
It controlled the disk motor. This allows R.A.
The disk motor can be servoed so as not to exceed the jitter absorption amount of M.

The above technique is described in Japanese Patent Application Laid-Open No. 59-90262.

(c) Problems to be Solved by the Invention However, conventionally, in order to detect the amount of data stored in the RAM, an arithmetic circuit for calculating the difference between the write address and the read address of an address counter that controls the address of the RAM has been used. This has the disadvantage of increasing the number of elements.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned points.
a first counter that determines the AM write address;
RAM (7) A second counter that determines the read address, a third counter that can preset the contents of the second counter (or the first counter), and counts by applying a clock pulse to the third counter. a fourth counter that counts the number of clock pulses until it matches the content of the first counter (or second counter) when the count value of the fourth counter is within a predetermined range; Increase or decrease the frequency division ratio of the frequency divider circuit built into the servo circuit of
and a control circuit that presets the first or second counter to a predetermined value when the value is outside the predetermined range.

(*) Effect: According to the above-mentioned means, the first counter receives the write request pulse 32LP generated based on the synchronization signal of the EFM signal.
The second counter counts up and specifies the read address by counting up the reference clock pulse from the crystal oscillation circuit, but the write address is within a predetermined area ζ ( For example, the "6" area) is larger. Therefore, if the count value of the second counter is preset to the 30th counter by the preset pulse PS generated at a certain timing, and then the clock pulse COMPCL is applied to the third counter to start counting, it will not work normally. If the disk is rotating, coincidence between the first and third counters is detected by six clock pulses COMPCL. In other words, the jitter absorption amount of the RAM can be determined based on the count value of the fourth counter when -, and the control circuit increases or decreases the frequency division ratio of the frequency divider circuit of the servo turntable based on the count value of the fourth counter. However, when the value is outside the predetermined range, the first counter is preset to a predetermined value and the RA is
Return the write and read addresses of M to their normal positions.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. 1st
The counter (FCTRH) (1) specifies the address area of the RAM (not shown) in which 24 information symbols and 8 parity symbols for one frame demodulated from the EFM signal are written. It is made up of bits. In addition, the count input CL of the first counter (1) has the following values:
A counter (
The carry output of FCTRL)<2) has been applied.

That is, the first counter (1) specifies the upper address of the RAM where one symbol for one frame is written, and the counter (2) specifies the lower address where one symbol is written in that address area. be. Here, the write request signal 32LP is set to PL in synchronization with the EFM signal.
Synchronous signal PLCK (4
, 3218M) 12), so the EFM
Due to the jitter in the signal, jitter also occurs in the counts of the counter (2) and the first counter (1).

- On the other hand, the second counter (XCTR) (3) is composed of 7 bits, and in order to read out the symbols for one frame written in the RAM, the address area where one frame worth of symbols is stored. Specify.

The count input CL of this second counter (3) contains a clock pulse ≠ 3M (2, 1609MH) generated from a reference clock pulse oscillated by a crystal oscillation circuit (not shown).
The carry output of the hexadecimal counter (TnSR) (5), which is continuously connected to the 49-decimal counter (49CTR) (4) that counts z), is no longer applied.

That is, the timing for signal processing of the symbol of one frame consists of timing frames T, ~T, each consisting of 49 timings t0 ~ tas, and when the processing of one frame is completed, the second counter (3) The count increases by 1", and the counting is extremely accurate because it is based on a crystal oscillator circuit.

The third counter (COMPCTR) (6) is a 7-bit presettable counter, and the second counter (COMPCTR) (6) is a 7-bit presettable counter.
) is applied to the preset input terminal, and the preset control input P is an AND gate (7) to which the timing signal T6 and the signal 5INT generated at the first timing t0 of each timing T, ~T, are applied. A preset pulse PS is applied to the clock CL, and a timing signal T5 and a timing t are applied to the clock CL.

~t4. Pulse 5Y output in synchronization with the timing of
The output signal COMPCL of the AND gate (8) to which NDCL is applied is applied. Fourth counter (CLCT
R) (9) is a 4-bit counter that counts the clock pulse COMPCL that is applied to and counted by the third counter (6), and the preset pulse PS is applied to the reset manual power R, and the clock pulse COMPCL is applied to the clock manual power CL. Pulse C
OMPCL is applied.

Furthermore, the 7-bit output of the first counter (1) and the 7-bit output of the third counter (6) are applied to a coincidence detection circuit (10), and the count values of each counter (1) and (6) are A match is detected. - The detection output DET of the matching detection circuit (10) and the output of the fourth counter (9) have been applied to the control circuit (11).

By the way, in the embodiment shown in FIG.
There is a difference of "6" frames between the write address to the RAM and the read address from the RAM. That is, when the disk is rotating at a normal linear velocity, the count value of the first counter (1) is always larger by "6" than the count value of the second counter (3). Therefore, the third
When the counter (6) counts six clock pulses COMPCL, the coincidence detection circuit (10) outputs a -coincidence detection output DE.
T should be able to be outputted, and the count value of the fourth counter (9) at that time should be "6'".Therefore, the control circuit (11) outputs the -match detection output DET. When the count value of the fourth counter (9) is determined, the frequency dividing ratio of the frequency dividing circuit (12) is increased or decreased.
As shown in the figure, the count value of the fourth counter (9) is "5"
~'7°'', it is assumed that the disk is rotating normally, and the frequency division ratio is not increased or decreased, and the fourth counter (
When the count value of 9) is between "2" and "4'", it is assumed that the rotation of the disk is slow, and a control signal (+) is output to increase the frequency division ratio. counter (9)
When the count value is between "8" and "10", it is assumed that the rotation of the disk has become faster and a control signal (-) for reducing the frequency division ratio is output. Furthermore, if the count value of the fourth counter (9) is outside the range of "2" to "10", it is assumed that the rotation of the disks is completely out of synchronization, and a muting signal MUTE is output. At the same time, an initial set pulse PS "6" is output.

Control signals (+) and (-) of the control circuit (11) are applied to a frequency dividing circuit (12) that constitutes a servo circuit of the disk motor. The frequency dividing circuit (12) is a divider that counts the synchronization signal PLCK of the EFM signal, and the frequency division output PLCK
PD is applied to the phase detection circuit (13) and generates a clock pulse φ4M (4, 3
Output XD of the frequency divider circuit (14) that divides the frequency (218MHz)
The phase is compared with IVPD. The frequency dividing ratio of this frequency dividing circuit (14) is 1-1, and the frequency dividing ratio of the frequency dividing circuit (12) is 588 when the control signals (+) and (-) are not applied. It has become. That is, the phase comparison is made for each frame, which is equal to the number of bits for one frame of the EFM signal, and the disk motor is controlled by the output of the phase detection circuit (13). - On the other hand, when the control signal (+) is output from the control circuit (11), the frequency division ratio of the frequency divider circuit (12) is -1
-, the disc motor is controlled in the direction of increasing rotation, and when the control signal (-) is output, the frequency division ratio of the frequency dividing circuit (12) becomes 587, and the disc motor is controlled in the direction of slowing down the rotation. . This control is performed once every 128 frames.

On the other hand, the initial set pulse PS ``6'' that can be output from the control circuit (11) is sent to the 0'' detection circuit (15) that detects when the count value of the second counter (3) becomes ``0''.
AND gate (1
6), and the output of the AND gate (16) is applied to the preset control power P of the first counter (1).

That is, the count value of the fourth counter (9) is "2" to "1o".
When the second counter (3) becomes "0" due to the initial set pulse PS '6' which is output when it is out of the range of ', '6' is preset to the first counter (1). Therefore, at this time, the write address to the RAM and the read address from the RAM are forced to the normal address positions.

Also, at this time, the symbols stored in the RAM are
Since it is doubtful whether the symbol is accurate, the muting signal MUTE from the control circuit (11) is applied to the circuit that sends the symbol to the DA converter circuit, thereby muting the symbols for a period of 128 frames to prevent the generation of noise.

In the circuit shown in FIG. 1, as shown in FIG.
Among T*, the count value of the second counter (3) is preset to the third counter (6) by the preset pulse PS output at timing t0 of timing T6. The clock pulse CO that can be generated by the pulse 5YNDCL output by
MPCL has a third counter (6) and a fourth counter (
9), and when the count values of the first counter (1) and the third counter (6) match, the fourth counter (9)
) can determine the state of the RAM.

(g) Effects of the Invention As described above, according to the present invention, there is no need for an arithmetic circuit that calculates write addresses to RAM and read addresses from RAM, and the remaining amount of RAM can be determined using only a simple counter. The advantage is that the number is significantly reduced. Furthermore, if the rotations of the disk motors are significantly out of synchronization, the generation of noise can be prevented and the address for accessing the RAM can be brought into a normal state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation. (1)...first counter, (2)...counter,
(3)...second counter, (4)...49-decimal counter, (5)...hexadecimal counter, (6)...third
counter, (9)...Fourth counter, (10)
...-match detection circuit, (11) ... control circuit, (1
2)... Frequency divider circuit, (13)... Phase detection circuit,
(14)...Frequency divider circuit, (15)..."O" detection circuit.

Claims (1)

[Claims] 1. Storing symbol data demodulated from the EFM signal read from the disk in a RAM, reading the symbol data from the RAM and deinterleaving it, and
In a signal processing circuit of a CD playback device that corrects the rotational speed of a disk motor based on the amount of data stored in the RAM, a first circuit that determines a write address of the RAM;
a second counter that determines the read address of the RAM; a third counter to which the contents of the second counter (or the first counter) are preset; and a clock pulse to the third counter. a fourth counter that counts the number of clock pulses until it matches the content of the first counter (or second counter) when the count value of the fourth counter is within a predetermined range; The frequency dividing ratio of the frequency dividing circuit built in the disk motor servo circuit is set to a reference value, or the frequency division ratio is increased or decreased within a predetermined value from the reference value, and when the frequency division ratio is outside the predetermined range, the first
1. A signal processing circuit for a CD playback device, comprising: a control circuit for presetting a predetermined value to a counter or a second counter.