JPS63220331A - Noise removal circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a noise removal circuit and can be applied to semiconductor integrated circuits.

BACKGROUND ART Microcomputers require noise removal circuits because noise contained in input signals causes malfunctions. Conventionally, noise removal circuits have been constructed of circuits as shown in FIG. FIG. 4 is a timing chart of the same circuit.

Id is a sampling clock input, 111'' is an input signal, 1o1 is a D flip-flop that latches the input signal in synchronization with the sampling clock, and 102 is a D flip-flop that holds the data latched by the previous stage latch circuit in synchronization with the sampling clock. This is a flip-flop.The outputs Q4 and Q2 of the D flip-flops 101 and 102 are
They are input in parallel to a circuit 201 and an fOR circuit 202, respectively. Each output Q of D flip-flop 101°102
1. If both Q2 are at high level, the ND circuit 20
1's output S becomes high level, R-S flip 70
301 pieces of data are set, and the output signal is 0. becomes high level.

In addition, each output Q4 of the D flip-flops 101 and 102
．． If both Q2 are low level, NOR circuit 202
The output R4 of R-8 flip-flop 301 becomes high level, the data of R-8 flip-flop 301 is reset, and its output signal 0 becomes low level. On the other hand, D flip 7o knob 101, 10
2 each output Q1. If the values of Q2 are different, the output signal 01 of the R-8 flip-flop 3o1 does not change.

Problems to be Solved by the Invention In such a conventional circuit, as shown in FIG. There is a drawback that if noise with a pulse width slightly wider than the pulse period of k is included in the input signal, a malfunction will occur in the output signal 01.

Means for Solving the Problems In order to solve the above problems, the present invention provides three or more stages of cascaded latch circuits that latch input signals in synchronization with a sampling clock, and a data signal of each stage of the cascaded latch circuits. This is a noise removal circuit equipped with a majority logic circuit having three or more inputs input in parallel.

Effect: According to the present invention, malfunctions due to noise contained in input signals can be prevented.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the noise removal circuit of the present invention. 101 to 104 are cascaded latch circuits of D flip-flops that sequentially latch the input signal I+ in synchronization with the sampling clock, namely, a 4-bit 7-foot register, and 200 is the input signal Q1 to Q1. When three or more inputs of Q4 are at high level, output terminal H is at high level and input terminal Q is at high level.
, ~A majority logic circuit whose output terminal outputs a high level when three or more inputs of Q4 are at a low level, 301
is an R-S flip-flop that latches output data. FIG. 2 is a timing chart of the circuit diagram of FIG.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2.

sampling clock. The D flip-flop 101 latches data on the input signal 1 in synchronization with the rising edge of k. At this time, the D flip-flop 102 latches data from one clock ago, the D flip-flop 103 latches data from two clocks ago, and the D flip-flop °1
04 latches data three clocks ago. If three or more of the data signals Q, ~Q4 of the D flip-flops in each stage are at high level, the majority logic circuit 200
performs data reset of the output data latch 301 and makes the output signal 01 high level. Still, each data signal Q1
If three or more of ~Q4 are low, the majority logic circuit 200 performs data re-cent of the output data latch 301, and the output signal 0. to low level. For example, even if the input signal signal contains noise, the sampling clock signal cannot be used. If the pulse noise is less than twice the period of k, the output signal is 0. does not generate a malfunction signal.

As described in detail, the present invention has great practical effects because it is less affected by noise contained in the input signal.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart of Fig. 1, Fig. 3 is a conventional circuit diagram, and Fig. 4 is a circuit diagram of the third embodiment.
3 is a timing chart of the figure. 1o1-104...D flip-flop (cascade latch circuit), 200...majority logic circuit, 2
01...mu ND circuit, 202...NO
R circuit, 301... Output latch. Figure 1 Figure 2

Claims (1)

[Claims] It is characterized by comprising three or more stages of follower latch circuits that latch input signals in synchronization with a sampling clock, and a majority logic circuit with three or more inputs that inputs data signals from each stage of the cascaded latch circuits in parallel. Noise removal circuit.