JPS6322717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the field to which the invention pertains The present invention relates to a clock generation circuit that switches between a synchronous sampling clock and an asynchronous sampling clock in encoding an image signal.

(2) Description of conventional technology The synchronization frequency accuracy of image signals ranges from less than ±30ppm like commercial television signals to VTRs.
The range is extremely wide, even up to nearly ±1000ppm like the output signal.

When encoding these signals, depending on the application, a DPCM encoding device and an interframe encoding device may be connected in series. Since interframe coding makes it possible to use the correlation between frames through synchronous sampling and to perform coding, it is preferable that the connected DPCM encoding device also performs encoding rather than synchronous sampling.

On the other hand, for signals with poor frequency accuracy such as VTR output signals, it is difficult to generate a clock that is phase-synchronized with the horizontal synchronization signal.
A DPCM encoding device has no choice but to perform asynchronous sampling.

In this way, when a DPCM encoding device requires both synchronous sampling and asynchronous sampling, it would be convenient if one encoding device could handle both.

Conventionally, the DPCM for synchronous sampling and the DPCM for asynchronous sampling have been configured separately, and therefore the clock generation circuits have also been configured separately depending on the DPCM used.

(3) Purpose of the Invention The present invention provides a method for encoding an image signal by using a synchronous sampling clock for an image signal whose synchronous frequency accuracy is within a predetermined standard, and for an image signal whose synchronous frequency accuracy is within a predetermined standard. It is characterized by automatically switching the clock to an asynchronous sampling clock, and its purpose is to provide a clock for an image signal encoding device that can encode a wide range of image signals, from commercial television signals to simple VTR signals. The purpose is to provide a generating circuit.

The drawings will be explained in detail below.

(4) Description of structure and operation of the invention FIG. 1 shows an embodiment of the invention, in which 1 is an image signal input terminal, 2 is a synchronization separation circuit, 3 is a phase synchronization oscillation circuit, 4 is an out-of-synchronization detection circuit, 5 is a clock switching signal generation circuit, 6 is a signal source switching timing signal input terminal, 7 is a switching circuit, 8 is an external clock input terminal, and 9 is a clock output terminal.

To operate this, an image signal input from the image signal input terminal 1 is supplied to the synchronous separation circuit 2,
Here, the horizontal synchronization signal is separated and the separated horizontal synchronization signal is supplied to the phase synchronization oscillation circuit 3. The phase synchronized oscillation circuit 3 receives the output of the synchronization separation circuit 2, generates a clock that is phase synchronized therewith, and outputs it to the out-of-synchronization detection circuit 4 and the switching circuit 7. The out-of-synchronization detection circuit 4 checks whether the frequency of the output signal of the phase-locked oscillation circuit 3 is within a predetermined range, and if it is out of this range, outputs an out-of-synchronization signal.

The clock switching signal generation circuit 5 is composed of, for example, a set/reset flip-flop.
It is set by the signal input from the signal source switching timing signal input terminal 6, set by the output signal of the out-of-synchronization detection circuit 4, and the output signal is sent to the switching circuit 7.
Send to. When this signal is “0”, the switching circuit 7
is connected to the output of the phase synchronized oscillation circuit 3, that is, the synchronous sampling clock, and when it is "1", the external clock input terminal 8 is connected, and the asynchronous sampling clock is sent to the clock output terminal 9.

FIG. 2 shows an embodiment of the out-of-sync detection circuit 4, in which 401 is a frequency/voltage conversion circuit, 402, 4
03 is a comparison circuit, 404 and 405 are reference voltage setting terminals, 406 and 409 are OR circuits, and 407 is an out-of-standard confirmation circuit, which detects a signal whose synchronous frequency is always out of the standard, such as in a VTR.
408 is a synchronous sampling protection circuit which prevents the broadcast television signal from switching to an asynchronous sampling clock due to loss of synchronization that occurs when switching cameras.

A frequency/voltage conversion circuit 401 counts the clocks supplied from the phase synchronized oscillation circuit 3, converts the frequency into a voltage value, and compares this with a predetermined reference voltage in comparison circuits 402 and 403. The reference voltage setting terminal 404 is +
A voltage corresponding to a frequency of 30 ppm is set, and the reference voltage setting terminal 405 is set to a voltage corresponding to a frequency of -30 ppm.

Comparison circuit 402 is frequency/voltage conversion circuit 40
When the output voltage of "1" is higher than the voltage set at the reference voltage setting terminal 404, an output "1" is generated. Similarly, the comparison circuit 403 includes the frequency/voltage conversion circuit 40
When the output voltage of "1" is lower than the voltage set at the reference voltage setting terminal 405, an output "1" is generated. OR
A circuit 406 receives the outputs of the comparison circuits 402 and 403.
Take OR.

Next, the out-of-standard confirmation circuit 407 will be explained. 4
10 is a monostable oscillation circuit, 411 is an OR circuit, 41
2 is set/reset flip flop, 4
13 is a counter, and 414 is an AND circuit.

These operations will be explained using the time chart shown in FIG. a represents the output of the OR circuit 406, and shows the case where two non-standard signal sources are connected in succession. b represents the output of the monostable oscillation circuit 410, which remains "1" for a predetermined fixed period from the rising edge of the signal shown in a.

c represents a signal supplied to the signal source switching timing signal input terminal 6; for example, when the present invention is used in a telecommunications network targeting wideband signals, the signal c is supplied from the exchange every time a call occurs; obtain. This explanation describes the case where this signal source switching timing signal is supplied from the outside.
It can be easily inferred that by checking the presence or absence of the output of the synchronization separation circuit 2, the signal source switching timing signal can be generated internally.

d is the output of the OR circuit 411, which causes the set/reset flip-flop 412
By setting , the counter 413 is set to a countable state.

The counter 413 counts the pulses supplied from the external clock input terminal 8, and when a predetermined number of pulses have been counted, the pulse shown at g is sent to the AND circuit 41.
4 and set/reset flip flop 4
Output to 12. As a result, the set/reset flip-flop 412 is reset.
The counter 413 enters a counting prohibited state. The _T1 period shown in e is a countable period. That is, if the phase synchronized oscillation circuit 3 continues to run free for the period _T1 , the input image signal is considered to be out of specification. This determination is made by the AND circuit 414, which generates an output shown at h.

Next, the synchronous sampling protection circuit 408 will be explained.
415 is a set/reset flip-flop, 416 is a monostable oscillation circuit, and 417 is a counter.

These operations will be explained using the time chart shown in FIG. a represents the output of the OR circuit 406, and shows the case where the camera switches from time to time in the broadcast television signal. If an out-of-synchronization occurs at the time of switching, it becomes "1".

Set/Reset Flip Flop 415
is set when the signal a becomes "1", and in response, the monostable oscillation circuit 416 starts operating and outputs the signal "1" to the signal line A for a predetermined period _{T2 .} At the end, a pulse is output to signal line B.

The counter 417 counts the output pulses of the OR circuit 406 generated within the _T2 period, and does not generate an output if the count is less than a predetermined threshold N. Therefore, no output is supplied to the OR circuit 409, and there is no switching to asynchronous sampling. However, if the count number exceeds N within the _T2 period, it is assumed that it is difficult to continue synchronous sampling, and a pulse is generated as shown in c. As a result, OR circuit 40
9. The switching circuit 7 operates via the clock switching signal generation circuit 5, and switches to the asynchronous sampling clock.

In the above explanation, the case where phase synchronization is performed with a horizontal synchronization signal has been described, but it can be easily inferred that a similar configuration can be applied to a circuit synchronized with a color burst.

(5) Explanation of effects As explained above, since the synchronous sampling clock and the asynchronous sampling clock are automatically switched and generated according to the input image signal, by using this, it is possible to encode one image. This has the advantage that the device can encode any image signal.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of an out-of-synchronization detection circuit, FIG. 3 is a time chart for explaining the operation of the out-of-standard confirmation circuit, and FIG. FIG. 3 is a diagram showing a time chart for explaining the operation of the synchronous sampling protection circuit. In the figure, 1 is an image signal input terminal, 2 is a synchronization separation circuit, 3 is a phase synchronization oscillation circuit, 4 is an out-of-synchronization detection circuit, 5 is a clock switching signal generation circuit, 6 is a signal source switching timing signal input terminal, and 7 is a synchronization separation circuit. In the switching circuit, 8 is an external clock input terminal, and 9 is a clock output terminal.

Claims (1)

[Claims] 1. A synchronization separation circuit that separates a synchronization signal from an input image signal, a phase synchronization oscillation circuit that generates a clock that is phase-synchronized with the synchronization signal supplied from the synchronization separation circuit, and a clock that receives the clock supplied from the phase synchronization oscillation circuit. , an out-of-sync detection circuit that detects when the frequency accuracy of the input image signal deviates from the standard; upon receiving an external signal indicating that the image signal source has been switched, resets the output signal with this signal;
A clock switching signal generation circuit sets an output signal based on a signal supplied from the out-of-synchronization detection circuit, and an output signal of the phase synchronized oscillation circuit is set based on the output signal of the clock switching signal generation circuit. 1. A clock generation circuit for encoding an image signal, comprising a switching circuit that switches between and outputs a clock signal.